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Cygwin綜合實現RISC-V出錯

RISC-V的例子都要求在LINUX下安裝VIVADO,比較麻煩,想在WINDOWS下用Cygwin試試 1.開啟cygwin,執行如下命令

export PATH=$PATH:/cygdrive/c/Xilinx/Vivado/2015.2/bin

2.從 github下克隆e200_opensource-master 3.從digilent下載arty-a7-35的board file並放到\Xilinx\Vivado\2015.2\data\boards\board_files目錄下 4.切換目錄並執行

cd d:/e200_opensource-master/fpga
make install CORE=e203

5.將\e200_opensource-master\fpga\artydevkit\script中的board.tcl開啟,將part_board做如下更改:

set part_board {digilentinc.com:arty-a7-35:part0:1.0}

6.生成bit檔案

make bit

結果報錯:

ERROR: [Vivado 12-172] File or Directory '/cygdrive/d/e200/fpga/install/rtl/core/e203_ifu_ift2icb.v' does not exist
INFO: [Common 17-206] Exiting Vivado at Thu Sep 13 11:10:16 2018...
make[1]: *** [Makefile:18:obj/system.bit] 錯誤 1 make[1]: 離開目錄“/cygdrive/d/e200/fpga/artydevkit” make: *** [common.mk:41:bit] 錯誤 2

但實際上該目錄下確實是有e203_ifu_ift2icb.v的,百思不得其解。