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FPGA的速度等級（speed grade）（1）

XILINX公司FPGASpartan 3E系列XC3S500E速度等級為4.但一直不知道是什麼意思.

通過學習知道,

(1)CPLD與FPGA的速度等級定義的區別

(2)不同的公司FPGA的速度等級

(3)同一個公司的不同時期的定義也是不一樣的,如XLINX公司

具體內容可以參考以下材料.也可以在GOOGLE裡輸入 FPGA SPEED GRADE

(4)對於xilinx公司的FPGA的速度等級定義，個人觀點：它不是以前所定義的其內部的一些邏輯單元訊號傳播所花的時間，而是一類內部邏輯器件的執行速度，這些邏輯器件執行時滿足一定要求的時鐘頻率．它沒有具體的物理的資料意義，只是一類內部邏輯器件的執行速度的的代號．

There is no consistent definition of a speed grade for all devices. Even for Xilinx,

speed grades mean different things depending on if you are referring to a FPGA or a CPLD. For CPLDs, speed grades represent the time it takes for logic to go through the device (eg. in <= out). So a -10 device means that the device is guaranteed to send a signal from an input pin thru to an output pin in under 10 nS. So for CPLDs, the lower the number, the faster the part is. This is standard for CPLDs across all vendors so this can be used for device comparison purposes.

what is the valve of standard grade(FPGA)

However for FPGAs, they don't use the same definition for speed grade. Originally speed grades for FPGAs represented the time through a look up table but now the speed grade doesn't actually repesent a timing path. I am not sure if it is the same for other vendors, but for Xilinx

FPGAs higher numbers are faster. Each speed grade increment is ~15% faster than the one before it. So a -5 is 10% faster than a -4 speed grade.

Determining the speed grade of Xilinx devices

Q:

I am having some trouble understanding the numbering system Xilinx uses for speed grade. Could someone explain what the numbers are and how to tell which speed grade is installed on my XS40. FWIW I have an XC4010XL FPGA. The available speed grade choices are -1, -2 -3, or -09.

A:

You usually see the speed grade imprinted on the chip on a line by itself. For an XC4000, you might see " 3C" printed on the chip. That means the chip has speed grade -3. (I think the "C" stands for commercial temperature range.)

For XC4000 devices, the number is roughly equivalent to the propagation delay through a CLB. So a -3 speed grade implies 3 ns of delay through a level of logic, -2 means 2 ns. Don't be mislead by -09, it actually means 0.9 ns of delay.

The situation changes with Spartan and Virtex devices. Now a larger number means the device is faster.

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FPGA的速度等級（speed grade）（2）

Question:

From: vlsigeek
Date Posted : 12/11/2004 4:42:49 AM Hi guys,

What is the speed grade in FPGA. What it tells actually.

Thanks in advance,

Soundar

Comments:

From: vlsi_giant
Posted : 12/27/2004 12:54:29 AM Hi
It is actually the min I/O delay for that device.
Ex: for altera MAX device EPM7128... -15
this -15 indicates this device has min of 15 ns. i/o delay.

yogesh

speed grade Category: FPGA Question: From: surekha29 Date Posted : 7/19/2006 5:19:41 AM While using xilinx synthesis tool, in the synthesis reports I found a term called speed grade : -6, what does this actually mean?? Comments: From: muthu_kumar Posted : 7/20/2006 12:53:49 AM Hi, Use this field to test a speed grade with your design. Changing the speed grade helps determine a need to target a faster device to meet your timing requirements, or if using a slower speed grade still meets timing constraints. Select a speed grade from the pull-down list, which contains the available speed grades for the target device. Changing the speed grade in the Options tab tests it with the design; it does not change the speed grade in your FPGA design file. regards muthukumar.p From: vikas Posted : 7/27/2006 6:06:01 AM THE FREQUENCY OF DESIGN DEPENDS UPON SELECTED DEVICESPEED GRADE. suppose u have design that is working on 50 mhz,with a device whose speed grade is 6. now if u want to work at 70 Mhz frequency.and with speed grade 6 u r not acheving that much frequency with that device.then if u take same device with more speed grade then this its sure that ur design fequncy will also increase but it is more costly then then the earlier. if still have any doubt ask dont hesitate [email protected] vikas lakhanpal engineer vlsi designs coral telecom From: vikas Posted : 7/27/2006 6:07:11 AM i think that is the importance of speed grade. From: vikas Posted : 7/27/2006 6:07:13 AM i think that is the importance of speed grade. From: surekha29 Posted : 7/28/2006 2:20:34 AM Thanks for ur comments Muthu Kumar and Vikas. In my search I have found my answer, n thought of sharing... Internal frequency is the speed at which CPLDs/FPGAs can perform operations or transfer data internally. The propagation delay is the time interval between the application of an input signal and the occurrence of the corresponding output in a logic circuit. Speed grade indicates the delay in nanoseconds (ns) through a macrocell in the device. For example, a device with a speed grade of –10 has a delay of 10 ns through a macrocell. Devices with low speed grade numbers run faster than devices with high-speed grade numbers. speed grade of -09 implies a delay of 0.9ns. From: muthu_kumar Posted : 7/30/2006 11:23:51 PM Hi surekha,Where u get these ideas?provide the source. i have doubt about your answers.myself and vikas going into the same direction i.e when the device speed grade is increase then the speed of the device also increase.but your answer is different.I warm welcome to all the readers.pls share your points about this question. regards muthukumar.p From: surekha29 Posted : 7/31/2006 2:12:06 AM Hello, I have seen the details at the following links. http://cpld.globalspec.com/ http://www.altera.com/products/devices/dev-format.html http://cpld.globalspec.com/LearnMore/Semiconductors/Programmable_Logic_Devices/CPLD I hope the definition of speed grade for FPGA and CPLD are the same. I think the minus indicates the samething, i.e., as the delay increases the speed(frequency) reduces. From: muthu_kumar Posted : 7/31/2006 11:44:50 PM Hi thanks ,to day i got the new idea from u. xilinx fpga point of view -7 speed grade device faster than -6 speed grade device. But altera cpld point of view -10 speed grade device slower than -9 speed grade device. ok -10 and -9 are denotes the macrocell propagation delay. but if u know any specification of -7 or -6 in FPGA.Anybody knows pls let me know. regards muthukumar.p From: gargji Posted : 8/2/2006 4:58:03 AM Hi Muthu, I can give you some more clearification about FPGA speed grades. In an FPGA the fabricator devides the devices in to some categories. Speed grade -7 means that there is a range of macrocell delay in FPGA which is kept in this category. But in cplds -10 means the macrocell delay is 10 ns. Hope the same is helpfull. rgds From: manish. Posted : 9/2/2006 5:15:56 PM surekha n all comment after checking this site http://www.xess.com/faq/M0000236.HTM From: gauravkshri Posted : 11/9/2006 1:14:49 AM hi guys, I just read ur comments. If I have been told to describle Speed grade in a sentence,I would say " Its a minimum i/o delay". This means a signal will take atleast this much of time to travel from i/p to o/p. From: gauravkshri Posted : 11/9/2006 1:21:26 AM hi, You usually see the speed grade imprinted on the chip on a line by itself. For an XC4000, you might see "3C" printed on the chip. That means the chip has speed grade -3. (I think the "C" stands for commercial temperature range.) For XC4000 devices, the number is roughly equivalent to the propagation delay through a CLB. So a -3 speed grade implies 3 ns of delay through a level of logic, -2 means 2 ns. Don't be mislead by -09, it actually means 0.9 ns of delay. The situation changes with Spartan and Virtex devices. Now a larger number means the device is faster. http://www.xess.com/faq/M0000236.HTM

轉自於：

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[合集] FPGA中，速度等級代表了什麼？
發信人: zhaoguangjie (趙廣傑), 信區: FPGATech
標  題: [合集] FPGA中，速度等級代表了什麼？
發信站: 水木社群 (Mon Mar 24 14:29:25 2008), 站內

☆─────────────────────────────────────☆
   pebble001 (pebble001) 於  (Wed Aug 29 14:02:29 2007)  提到:


在altera的FPGA中，速度等級具體代表什麼意義？是內部最高執行頻率的限制嗎？

比如-6，-7與-8的EP2C8,在使用時具體有什麼區別？

謝謝！




☆─────────────────────────────────────☆
   honest41 (當索愛遇見諾基亞) 於  (Wed Aug 29 16:43:30 2007)  提到:

altera的速度等級都是比較抽象的等級，不好說具體表示有多快，不過值越小越快,8是最慢的
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等級具體代表什麼意義？是內部最高執行頻率的限制嗎？
: 比如-6，-7與-8的EP2C8,在使用時具體有什麼區別？
: 謝謝！
: ...................



☆─────────────────────────────────────☆
   WeiWei (TISSOT) 於  (Wed Aug 29 16:44:02 2007)  提到:


是不是時延特性？

【 在 honest41 (當索愛遇見諾基亞) 的大作中提到: 】
: altera的速度等級都是比較抽象的等級，不好說具體表示有多快，不過值越小越快,8是最慢的




☆─────────────────────────────────────☆
   pebble001 (pebble001) 於  (Wed Aug 29 17:52:23 2007)  提到:


那在具體選型時怎麼考慮呢？

-7與-8之間具體有什麼差異呢？

選晶片時就選能得到的最快的？

謝謝！

【 在 honest41 (當索愛遇見諾基亞) 的大作中提到: 】
: altera的速度等級都是比較抽象的等級，不好說具體表示有多快，不過值越小越快,8是最慢的





☆─────────────────────────────────────☆
   Anmywang (anmy) 於  (Wed Aug 29 18:00:28 2007)  提到:

-6的速度是最快的，-8是最慢的。
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等級具體代表什麼意義？是內部最高執行頻率的限制嗎？
: 比如-6，-7與-8的EP2C8,在使用時具體有什麼區別？
: 謝謝！





☆─────────────────────────────────────☆
   leuse (還是太沖動啊) 於  (Wed Aug 29 18:16:42 2007)  提到:

應該是代表片內的最大延時，-8就表示8ns
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等級具體代表什麼意義？是內部最高執行頻率的限制嗎？
: 比如-6，-7與-8的EP2C8,在使用時具體有什麼區別？
: 謝謝！
: ...................



☆─────────────────────────────────────☆
   newbeesile (blackjack他是誰 ) 於  (Wed Aug 29 18:37:41 2007)  提到:

cpld有這個說法 FPGA基本上沒有一個特定指標跟這個等級相關了
【 在 leuse (還是太沖動啊) 的大作中提到: 】
: 應該是代表片內的最大延時，-8就表示8ns




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   InterRonaldo (羅那爾多在Inter) 於  (Wed Aug 29 19:08:28 2007)  提到:

補充下，xilinx的FPGA是越大越快

【 在 Anmywang (anmy) 的大作中提到: 】
: -6的速度是最快的，-8是最慢的。




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   FabioCapello (我的心看上去是紅的) 於  (Wed Aug 29 19:08:40 2007)  提到:

Xilinx是那樣吧.
Altera代表的是ns.

【 在 honest41 (當索愛遇見諾基亞) 的大作中提到: 】
altera的速度等級都是比較抽象的等級，不好說具體表示有多快，不過值越小越快,8是最慢的
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等級具體代表什麼意義？是內部最高執行頻率的限制嗎？
: 比如-6，-7與-8的EP2C8,在使用時具體有什麼區別？
: 謝謝！
: ...................



☆─────────────────────────────────────☆
   honest41 (當索愛遇見諾基亞) 於  (Wed Aug 29 19:39:01 2007)  提到:

選型時主要還是考經驗估計吧，不過同種型號各個速度等級的封裝，資源都是一樣的，所以不影響做板。到時候大不了-8的不夠用-6
【 在 pebble001 (pebble001) 的大作中提到: 】
: 那在具體選型時怎麼考慮呢？
: -7與-8之間具體有什麼差異呢？
: 選晶片時就選能得到的最快的？
: ...................



☆─────────────────────────────────────☆
   flyingcowboy (敢笑“敢笑楊過不痴情”不痴情) 於  (Wed Aug 29 20:17:04 2007)  提到:

速度快的太難買了
【 在 honest41 (當索愛遇見諾基亞) 的大作中提到: 】
: 選型時主要還是考經驗估計吧，不過同種型號各個速度等級的封裝，資源都是一樣的，所以不影響做板。到時候大不了-8的不夠用-6





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   pebble001 (pebble001) 於  (Wed Aug 29 22:11:02 2007)  提到:


有的封裝只有一個速度等級
換速度等級就得換封裝，重新畫板子啊~


【 在 honest41 (當索愛遇見諾基亞) 的大作中提到: 】
: 選型時主要還是考經驗估計吧，不過同種型號各個速度等級的封裝，資源都是一樣的，所以不影響做板。到時候大不了-8的不夠用-6





☆─────────────────────────────────────☆
   pebble001 (pebble001) 於  (Wed Aug 29 22:17:13 2007)  提到:

還是沒明白速度等級到底和什麼相關，代表了什麼:(

比如本該用-7的，我用成了-8的，會有什麼壞處？

是片內最高執行頻率降低了？還是什麼其他的影響？



【 在 honest41 (當索愛遇見諾基亞) 的大作中提到: 】
: 選型時主要還是考經驗估計吧，不過同種型號各個速度等級的封裝，資源都是一樣的，所以不影響做板。到時候大不了-8的不夠用-6





☆─────────────────────────────────────☆
   oBigeyes (以不變應萬變) 於  (Wed Aug 29 22:18:06 2007)  提到:

片內速度和io速度可能都影響

【 在 pebble001 (pebble001) 的大作中提到: 】
: 還是沒明白速度等級到底和什麼相關，代表了什麼:(
: 比如本該用-7的，我用成了-8的，會有什麼壞處？
: 是片內最高執行頻率降低了？還是什麼其他的影響？
: ...................



☆─────────────────────────────────────☆
   tangtseng (土豆) 於  (Wed Aug 29 22:36:12 2007)  提到:

沒有特別的含義。只是在fpga生產後進行了篩選，分處了三個等級，然後標不同的價格。
不同級別只有相對比較的意思，沒有延遲的概念。我是這麼理解的。他們的FAE也是這麼解釋的。
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等級具體代表什麼意義？是內部最高執行頻率的限制嗎？
: 比如-6，-7與-8的EP2C8,在使用時具體有什麼區別？
: 謝謝！





☆─────────────────────────────────────☆
   djay (伊泰（900948）) 於  (Sat Sep  8 15:55:22 2007)  提到:

大家都是做FPGA應用的麼,還要畫板子?
我們用的一般都是別人公司做好的,比如美國的DINI和瑞典的HARDY公司的
【 在 pebble001 (pebble001) 的大作中提到: 】
: 有的封裝只有一個速度等級
: 換速度等級就得換封裝，重新畫板子啊~




☆─────────────────────────────────────☆
   JDAM (billow2) 於  (Mon Sep 17 16:46:20 2007)  提到:

記得好像是0.X納秒吧...
當時做個專案，用EP1C12-8俊龍的介紹說-8是每過一個LUT0.8ns，好像
【 在 pebble001 (pebble001) 的大作中提到: 】
: 在altera的FPGA中，速度等級具體代表什麼意義？是內部最高執行頻率的限制嗎？
: 比如-6，-7與-8的EP2C8,在使用時具體有什麼區別？
: 謝謝！

=======================================================================================

xilinx fpga speed grade

Can anyone please explain what a speed grade is?
If i tell you my bicycle has a speed grade of 29, you'll probably say something like: "Good for you.", but you wouldn't have a clue about what i just said.
So, can you explain to me how i should see the speed grades.
What do they stand for?
Who defines the speed grades?
Can i compare the speed grades between manufacturers?

I can't seem to be able to find anything about the subject anywhere...
There is no consistent definition of a speed grade for all devices. Even for Xilinx, speed grades mean different things depending on if you are referring to a FPGA or a CPLD. For CPLDs, speed grades represent the time it takes for logic to go through the device (eg. in <= out). So a -10 device means that the device is guaranteed to send a signal from an input pin thru to an output pin in under 10 nS. So for CPLDs, the lower the number, the faster the part is. This is standard for CPLDs across all vendors so this can be used for device comparison purposes.

However for FPGAs, they don't use the same definition for speed grade. Originally speed grades for FPGAs represented the time through a look up table but now the speed grade doesn't actually repesent a timing path. I am not sure if it is the same for other vendors, but for Xilinx FPGAs higher numbers are faster. Each speed grade increment is ~15% faster than the one before it. So a -5 is 10% faster than a -4 speed grade.

Arthur
Jasper, As Arthur indicated, it is a relative term that is really dependent on the specific family: -for CPLDs, it is generally pin-to-pin delays in nanoseconds (lower # = faster) -for old Xilinx FPGAs (pre-Virtex), lower # was faster -for modern (Virtex and later) FPGAs, the higher # is faster. The speed grade influences a variety of timing paramters in the FPGA, including fabric (slice), multiplier/DSP48x, BlockRAM, I/O, and other resources parameters. You really need to consult the specific datasheet to see specific details for timing based on associated speed grades. For example, Virtex-4 speed grades are -10 (slowest), -11, and -12 (fatest) Virtex-5 spede grades are -1 (slowest), -2, and -3 (fastest) There is no correlation between these numbers. It is really a relative metric of performance within a specific family. Cheers, bt

===================================================================

最初接觸speed grade這個概念時，很是為Altera的-6、-7、-8速度等級逆向排序的方法困惑過一段時間。不很嚴密地說，“序號越低，速度等級越高”這是Altera FPGA的排序方法，“序號越高，速度等級也越高”這是Xilinx FPGA的排序方法。 riple

從那時起，就一直沒搞明白speed grade是怎麼來的，唯一的概念是：同一款晶片可以有多個速度等級，不同的速度等級代表著不同的效能，不同的效能又導致芯片價格的巨大差異。腦子裡總有一個模模糊糊的推測：FPGA廠家為了提高利潤，專門給同一款晶片生產了不同的速度等級。 riple

直到一年前和一位學過IC設計的同事hammer討論這一問題時，才有了新的認識：對FPGA廠家來說，為了得到同一款晶片的不同速度等級而專門設計不同的晶片版圖是不划算的；所以晶片的速度等級不應該是專門設計出來的，而應該是在晶片生產出來之後，實際測試標定出來的；速度快的晶片在總產量中的比率低，價格也就相應地高。 riple

這一解答很是合理，糾正了我

的一個錯誤認識。但是我仍然有兩點困惑：1. 是什麼因素導致了同一批晶片的效能差異；2. 如果因素已知，為什麼不人為控制這些因素，提高高速晶片的產率，達到既增加晶片廠商的利潤又降低高速芯片價格的目的呢。 riple

前些天在部落格裡看到huge朋友的一篇FPGA speed grade，激發了我進一步探索上述問題的動力。通過在網路上搜索，逐步得到了以下一些認識： riple

1. 晶片的速度等級決定於晶片內部的門延時和線延時，這兩個因素又決定於電晶體的長度L和容值C，這兩個數值的差異最終決定於晶片的生產工藝。怎樣的工藝導致了這一差異，我還沒找到答案。 riple

2. 在晶片生產過程中，有一個階段叫做speed binning。就是採用一定的方法、按照一組標準對生產出來的晶片進行篩選和分類，進而劃分不同的速度等級。“測試和封裝”應該就包含這一過程。 riple

    關於speed binning的技術有很多專利： riple

4. 晶片的等級可以在測試後加以具體調整和改善，在儲存器晶片的生產中這一技術應用很廣泛。 riple

5. 晶片生產的過程是充滿各種變數的，生產過程可以得到控制，但是控制不可能精確到一個分子、一個原子，產品質量只能是一個統計目標。同一個wafer上的晶片會有差異，即使是同一晶片的不同部分也是有差異的。速度等級是一個統計數字，反映了一批晶片的某些共同特性，不代表個別晶片的質量。而且由於某些晶片的測試是抽樣進行的，也不排除個別晶片的個別性能會低於標定的速度等級。不過，據說FPGA的測試是極嚴格的，很可能我們拿到手的晶片個個都經過了詳盡的測試。這也是FPGA芯片價格高於普通晶片的原因。 riple

6. 同一等級的晶片中的絕大多數，其效能應該高於該速度等級的劃分標準。這也是為什麼在FPGA設計中，有少許時序分析違規的設計下載到晶片中仍然能夠正常執行的原因（時序分析採用的模型引數是晶片的統計引數，是最保守也是最安全的）。不過，由於同一等級的晶片仍然存在效能差異，存在時序違規但是單次測試成功的FPGA設計不能確保在量產時不在個別晶片上出現問題（出了問題就要返修或現場調查，成本一下子就上去了）。所以，還是要把時序收斂了才能放心量產，這就是工程標準對產品質量的保證。 riple

7. 概率和統計學源於工程實踐，對工程實踐又起到了巨大的指導作用。工程實踐中的標準都是前人經驗教訓的積累，是人類社會的寶貴精神財富。 riple

8. 現實世界是模擬的，不是數字的。在考察現實問題時，我們這些數字工程師和軟體工程師應該拋棄“一是一、〇是〇”的觀念，用連續的眼光看待這個連續變化的真實世界。 riple

9. 晶片生產過程中的不確定性導致了晶片的效能差異，這一差異影響了晶片的價格，價格和效能的折中又影響了我們這些FPGA設計工程師在器件選型、設計方法上的決策，我們生產的產品的價效比決定了產品的銷售，產品的銷量又決定了晶片的採購量，採購量又影響了晶片的採購價格...。原子、分子級別上的差異，就這樣一級一級地傳遞和放大。人類社會就是這樣環環相扣，互相制約的。嘿，真是神奇！