---- Power modes

The power domains can be controlled independently to give different combinations of powered-up and powered-down domains. (Power domain 的控制是獨立的，可以有不同的上下電結合)

However, only some combinations are valid and supported.(只有一些結合是支援並有效的)The following table describes the supported power domain states for individual cores. The power domain state in each core is independent of all other cores.

1、Run mode

Run mode is the normal mode of operation in which all of the functionality of the processor is available. 

2、Standby mode

When a core is in standby mode, it is architecturally clock gated at the top of the clock tree. The clock is then cut from all registers in the core. This mode is also known as WFI(wait for interrupt) or WFE(wait for event). 

---- Core內暫存器的clock被關掉。

Each individual core in the cluster can be put into standby mode separately from the other cores.

---- Core Wait for Interrupt (WFI)

WFI is a feature of the ARMv8-A architecture that puts the core in a low-power state by disabling most of the clocks in the core while keeping the core powered up. 

通過關掉core的大部分clock，讓core進入low-power狀態，但是core不掉電。

Apart from a small dynamic power overhead on the logic to enable the core to wake up from WFI low-power state, this reduces the power drawn to static leakage current only. 

(小部分的動態功耗在邏輯電路上，可以將core從low power狀態喚醒，減少靜態漏電電流)

Software indicates that the core can enter the WFI low-power state by executing the WFI instruction. When the core is executing the WFI instruction, the core waits for all instructions in the core to retire before entering the idle or low-power state. (在進入idle或low-power狀態之前，執行完core內的所有指令)

The WFI instruction ensures that all explicit memory accesses that occurred before the WFI instruction in program order have retired. In addition, the WFI instruction ensures that store (store from a register into memory ) instructions have updated the cache or have been issued to the L3 memory system.

While the core is in WFI low-power state, the clocks in the core are temporarily enabled without causing

the core to exit WFI low-power state when any of the following events are detected:

臨時的enable core的clock不會引起core從WFI狀態退出，當檢測到以下任何一個事件時：

1)   An L3 snoop (探聽) request that must be serviced by the core data caches.

2)   A cache or TLB maintenance operation that must be serviced by the core L1 instruction cache, data cache,TLB, or L2 cache.

3)   An APB access to the debug or trace registers residing in the core power domain. Exit from WFI low-power state occurs when the core detects a reset or one of the WFI wake up events.

---- Core wait for event (WFE)

WFE is a feature of the ARMv8-A architecture that uses a locking mechanism (一種鎖機制) based on events to

put the core in a low-power state by disabling most of the clocks in the core while keeping the core powered up.

Apart from a small dynamic power overhead (小部分的動態功耗在邏輯電路上，可以將core從low power狀態喚醒) 

on the logic to enable the core to wake up from WFE low-power state, this reduces the power drawn to static

leakage current only. (減少靜態漏電電流)

---------同上

Exit from WFE low-power state occurs when the core detects a reset, the assertion of the EVENT1input signal, 

or one of the WFE wake-up events.

3、Shutdown mode (斷電)

Ananke supports a full shutdown mode, where power can be removed completely, and no state is retained.

The shutdown can be for either the whole cluster or just for an individual core, (可以整個cluster掉電，也可以是

單個core掉電) which allows other cores in the cluster to continue operating.

To avoid losing data, the cores within the cluster and the cluster itself must be taken out of coherence.