VHDL編寫二位數值比較器
阿新 • • 發佈:2020-11-25
此文轉載自:https://blog.csdn.net/ws15168689087/article/details/109992986
VHDL編寫二位數值比較器
二位數值比較器是由四個輸入端和三個輸出端組成的比較器,實現兩個二位二進位制數大小的比較(用高低電平來表示輸入輸出)真值表如下:
(xx表任意狀態)
因此設計時,定義4個輸入端和3個輸出端的實體,分別為A1A0,B1B0和f1(a>b)f2(a<b)f3(a=b)
具體程式碼如下:
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY homework2 IS PORT(A1:IN STD_LOGIC; --定義4個輸入端和3個輸出端 A0:IN STD_LOGIC; B1:IN STD_LOGIC; B0:IN STD_LOGIC; f1:OUT STD_LOGIC; f2:OUT STD_LOGIC; f3:OUT STD_LOGIC); END homework2; ARCHITECTURE HA OF homework2 IS SIGNAL tmp:STD_LOGIC_VECTOR(3 DOWNTO 0);--定義一個訊號陣列 BEGIN tmp<=A1 & B1 & A0 & B0; --用&連線四個輸入值,並賦值給tmp PROCESS(tmp) BEGIN CASE tmp IS --CASE語句實現具體程式碼 WHEN "0000" =>f1<='0';f2<='0';f3<='1'; WHEN "0001" =>f1<='0';f2<='1';f3<='0'; WHEN "0010" =>f1<='1';f2<='0';f3<='0'; WHEN "0011" =>f1<='0';f2<='0';f3<='1'; WHEN "0100" =>f1<='0';f2<='1';f3<='0'; WHEN "0101" =>f1<='0';f2<='1';f3<='0'; WHEN "0110" =>f1<='0';f2<='1';f3<='0'; WHEN "0111" =>f1<='0';f2<='1';f3<='0'; WHEN "1000" =>f1<='1';f2<='0';f3<='0'; WHEN "1001" =>f1<='1';f2<='0';f3<='0'; WHEN "1010" =>f1<='1';f2<='0';f3<='0'; WHEN "1011" =>f1<='1';f2<='0';f3<='0'; WHEN "1100" =>f1<='0';f2<='0';f3<='1'; WHEN "1101" =>f1<='0';f2<='1';f3<='0'; WHEN "1110" =>f1<='1';f2<='0';f3<='0'; WHEN "1111" =>f1<='0';f2<='0';f3<='1'; END CASE; END PROCESS; END HA;
模擬結果如下: