技術標籤：數字邏輯verilog

程式碼：

module counter23_69(reset,clk,mid_H,mid_L,mid_L_cy);

    input reset,clk;
    output[3:0] mid_H,mid_L;
    output mid_L_cy;
    reg[3:0] mid_H,mid_L;
    wire mid_L_cy;
    assign mid_L_cy=(mid_L==4'd9)?1:0;
    always @ (posedge clk)
		begin
        	if(reset) mid_L<=4'd3;
 

        	else if(mid_L_cy==1) 
                 begin
                     if(mid_H==4'd6) mid_L<=4'd3;
                     else mid_L<=4'd0;
                 end
        	else mid_L<=mid_L+1;
    	end
    always @ (posedge clk)
		begin
        	if(reset) mid_H<=4'd2;
        	else if(mid_L_cy==
 
1)
				begin
            		if(mid_H==4'd6) mid_H<=4'd2;
            		else mid_H<=mid_H+1;
        		end
        	else mid_H<=mid_H;
		end

endmodule

說明：

1、 僅設定一個眼位，足夠用了。
2、 高位是否變化通過低眼位判斷，即：只有在 mid_L_cy==1 時高位才能變化。

注意：此程式碼不夠完善，僅能解決“XX-X9”的計數器（比如此題，把69變成68就缺條件了）。完善程式碼見下篇。