技術標籤：狀態機verilogfpga人工智慧

1、狀態機（state machine）:有限狀態機（FSM）是指在有限個狀態之間按照以一定規律轉換的時序電路。

2、常用的狀態機有 Mealy狀態機和Moore狀態機：他們之間的區別，mealy狀態機的輸出與輸入有關，Moore狀態機與輸入無關

3、狀態機的設計，四段論

狀態空間設計

狀態跳轉模式

Nextstate判斷

Next action

狀態空間定義：

parameter SLEEP = 2'b00;

parameter STUDY = 2'b01;

parameter EAT = 2'b10;

paramter AMUSE = 2'b11;

reg [1:0] current_state;

reg [1:0] next_state;



parameter SLEEP = 2'b1000;

parameter STUDY = 2'b0100;

parameter EAT = 2'b0010;

paramter AMUSE = 2'b0001;

reg [1:0] current_state;

reg [1:0] next_state;
 

狀態跳轉（時序邏輯，非阻塞non blocking）

always @(posedge clk or negedge rst_n) begin

   if(! rst_n)

      current_state <=SLEEP;

   else

      current_state <= next_state;

end

下一個狀態判斷（組合邏輯block）

always @(current_state or input_signals) begin

   case (current_state)

        SLEEP: begin

              if (clock_alarm)

                   next_state = STUDY;

              else

                   next_state = SLEEP;

        end

        STUDY：begin

                  if (lunch_time)

                   next_state = EAT;

              else

                   next_state = STUDY;//if else 要配對，避免latch鎖存

        end
          
        EAT: begin

              if (clock_alarm)

                   next_state = STUDY;

              else

                   next_state = AMUSE;

        end

        AMUSE：begin

                  if (sleep_time)

                   next_state = SLEEP;

              else

                   next_state = STUDY;//if else 要配對，避免latch鎖存

        end
end
 

各個狀態的動作

wire read_book;
assign read_book =(current_state == STUDY)? 1'b1 :1'b0;

always @(current_state )begin
    if(current_state == STUDY)
        read_book = 1;
    else
        read_book = 0; //blocking 賦值
end

三段式（輸出組合邏輯後+時序邏輯）