華大微控制器中斷號可以先初始化好中斷對應的中斷號

void InitMcu_Nvic(void)
{
// set interrupt event
M4_INTC->SEL0_f.INTSEL = INT_WDT_REFUDF;
M4_INTC->SEL1_f.INTSEL = INT_EMB_GR0;
M4_INTC->SEL2_f.INTSEL = INT_EMB_GR1;
M4_INTC->SEL3_f.INTSEL = INT_EMB_GR2;
M4_INTC->SEL4_f.INTSEL = INT_EMB_GR3;
M4_INTC->SEL5_f.INTSEL = INT_ADC1_EOCA;
M4_INTC->SEL6_f.INTSEL = INT_ADC1_EOCB;
M4_INTC->SEL7_f.INTSEL = INT_ADC2_EOCA;
M4_INTC->SEL8_f.INTSEL = INT_ADC2_EOCB;
M4_INTC->SEL9_f.INTSEL = INT_TMR41_GUDF;
M4_INTC->SEL10_f.INTSEL = INT_TMR42_GUDF;
M4_INTC->SEL11_f.INTSEL = INT_TMR43_GUDF;

M4_INTC->SEL12_f.INTSEL = INT_USART3_RI;
M4_INTC->SEL13_f.INTSEL = INT_USART3_TI;
M4_INTC->SEL14_f.INTSEL = INT_USART3_TCI;

M4_INTC->SEL15_f.INTSEL = INT_TMR02_GCMA;
M4_INTC->SEL16_f.INTSEL = INT_TMR02_GCMB;

// clear pending IRQ
NVIC_ClearPendingIRQ(Int000_IRQn); ///< software watch dog
NVIC_ClearPendingIRQ(Int001_IRQn); ///< EMI group0 for Timer6
NVIC_ClearPendingIRQ(Int002_IRQn); ///< EMI group1 for Timer41
NVIC_ClearPendingIRQ(Int003_IRQn); ///< EMI group2 for Timer42
NVIC_ClearPendingIRQ(Int004_IRQn); ///< EMI group3 for Timer43
NVIC_ClearPendingIRQ(Int005_IRQn); ///< ADC1 scan sequence A completion interrupt
NVIC_ClearPendingIRQ(Int006_IRQn); ///< ADC1 scan sequence B completion interrupt
NVIC_ClearPendingIRQ(Int007_IRQn); ///< ADC2 scan sequence A completion interrupt
NVIC_ClearPendingIRQ(Int008_IRQn); ///< ADC2 scan sequence B completion interrupt
NVIC_ClearPendingIRQ(Int009_IRQn); ///< Timer41 CNT interrupt
NVIC_ClearPendingIRQ(Int010_IRQn); ///< Timer42 CNT interrupt
NVIC_ClearPendingIRQ(Int011_IRQn); ///< Timer43 CNT interrupt
NVIC_ClearPendingIRQ(Int012_IRQn);
NVIC_ClearPendingIRQ(Int013_IRQn);
NVIC_ClearPendingIRQ(Int014_IRQn);
NVIC_ClearPendingIRQ(Int015_IRQn);
NVIC_ClearPendingIRQ(Int016_IRQn);


//set IRQ priority
NVIC_SetPriority(Int000_IRQn, 1); ///< software watch dog
NVIC_SetPriority(Int001_IRQn, 2); ///< EMI group0 for Timer6
NVIC_SetPriority(Int002_IRQn, 2); ///< EMI group1 for Timer41
NVIC_SetPriority(Int003_IRQn, 2); ///< EMI group2 for Timer42
NVIC_SetPriority(Int004_IRQn, 2); ///< EMI group3 for Timer43
NVIC_SetPriority(Int005_IRQn, 3); ///< ADC1 scan sequence A completion interrupt
NVIC_SetPriority(Int006_IRQn, 3); ///< ADC1 scan sequence B completion interrupt
NVIC_SetPriority(Int007_IRQn, 3); ///< ADC2 scan sequence A completion interrupt
NVIC_SetPriority(Int008_IRQn, 3); ///< ADC2 scan sequence B completion interrupt
NVIC_SetPriority(Int009_IRQn, 4); ///< Timer41 CNT interrupt
NVIC_SetPriority(Int010_IRQn, 4); ///< Timer42 CNT interrupt
NVIC_SetPriority(Int011_IRQn, 4); ///< Timer43 CNT interrupt
NVIC_SetPriority(Int012_IRQn, 4);
NVIC_SetPriority(Int013_IRQn, 4);
NVIC_SetPriority(Int014_IRQn, 4);
NVIC_SetPriority(Int015_IRQn, 4);
NVIC_SetPriority(Int016_IRQn, 4);



// enable IRQ
NVIC_EnableIRQ(Int000_IRQn); ///< software watch dog
NVIC_EnableIRQ(Int001_IRQn); ///< EMI group0 for Timer6
NVIC_EnableIRQ(Int002_IRQn); ///< EMI group1 for Timer41
NVIC_EnableIRQ(Int003_IRQn); ///< EMI group2 for Timer42
NVIC_EnableIRQ(Int004_IRQn); ///< EMI group3 for Timer43
NVIC_EnableIRQ(Int005_IRQn); ///< ADC1 scan sequence A completion interrupt
NVIC_EnableIRQ(Int006_IRQn); ///< ADC1 scan sequence B completion interrupt
NVIC_EnableIRQ(Int007_IRQn); ///< ADC2 scan sequence A completion interrupt
NVIC_EnableIRQ(Int008_IRQn); ///< ADC2 scan sequence B completion interrupt
NVIC_EnableIRQ(Int009_IRQn); ///< Timer41 CNT interrupt
NVIC_EnableIRQ(Int010_IRQn); ///< Timer42 CNT interrupt
NVIC_EnableIRQ(Int011_IRQn); ///< Timer43 CNT interrupt
NVIC_EnableIRQ(Int012_IRQn);
NVIC_EnableIRQ(Int013_IRQn);
NVIC_EnableIRQ(Int014_IRQn);
NVIC_EnableIRQ(Int015_IRQn);
NVIC_EnableIRQ(Int016_IRQn);

}