verilog中支援signed 資料型別，即支援負數的處理。此時參與運算的各個數均應是signed型別，且資料位寬相同(若位寬不相同，則應手動將其擴充套件為位寬相同，具體做法就是將最高位的符號位進行擴充套件),且運算結果要比運算數的位數大以防止溢位。以下用兩個小例子進行說明。細節可參考此篇文章：http://www.cnblogs.com/oomusou/archive/2009/10/31/verilog_signed_overflow.html

Examp 1.

1. module top(clk,a,b,c);
2. input clk;
3. input signed [7:0] a;
4. input signed [7:0] b;
5. output reg signed [8:0] c;
7. always@(posedge clk)
8. begin
9. if((a-b)< 0)
10. c <= b - a;
11. else if ((b-a)==0)
12. c <= 0;
13. else
14. c <= a - b;
15. end
17. endmodule

testbench:

1. module sim_top ;
3. reg clk;
4. reg signed [7:0] a;
5. reg signed [7:0] b;
6. wire signed [8:0] c;
8. initial begin
9. clk= 0;
10. a=0;
11. b=8;
12. forever clk=#5 ~clk ;
13. end
15. always@(posedge clk)
16. begin
17. a<=a+2;
18. b<=b+1;
19. end
21. top my_top(
22. .clk(clk),
23. .a(a),
24. .b(b),
25. .c(c));
27. endmodule

模擬結果圖：

Examp 2：

1. module top(clk,a,b,c);
2. input clk;
3. input signed [7:0] a;
4. input signed [7:0] b;
5. output reg signed [8:0] c;
7. always@(posedge clk)
8. begin
9. /* if((a-b)< 0)
10. c <= b - a;
11. else if ((b-a)==0)
12. c <= 0;
13. else*/
14. c <= a - b;
15. end
17. endmodule

testbench同上。

模擬結果：