https://dspace.mit.edu/handle/1721.1/16674

The core is approximately 27K gate count, runs at a maximum of 250 MHz, and is synthesized to a current standard technology.

The verification portion of this thesis posed quite a challenge. The Bridgeimplementation ended up with 1150 input ports and 1061 output ports due to theinterfaces of the vendor’s PCI Express and PCIX Interfaces. With only one person tocreate a verification environment from scratch, a hierarchical approach was taken to finderrors early since bugs are difficult to find and fix at the system level.

A Design Compiler was used to synthesize the PCIEXB Verilog code into a gate-level netlist targeting a current IBM ASIC technology.

Synthesizing the Bridge involved making TCL scripts that were read by the DesignCompiler.

A Verilog netlist representation of the Bridge is the final result of the synthesis.

Many inexperienced engineers often run into problems with synthesis during their first design project. Knowing this is the case, efforts were made to fix these mistakes early on in the development process. 1. Combinational logic was coded in assign statementsrather than in an always block for multiple reasons; 2.Synthesize Early and Often.

和開發軟體還是有相像之處的：1. 不要留下沒初始化的變數，但不要在for迴圈的內層memset(ary, 0, 1GB); 2. Debug/Run earyly and often, 不要"我的程式Debug模式沒錯，Release模式一執行就crash，總共就7~8000行，你幫我解決下……"