日常記錄（74）其它
阿新 • • 發佈：2022-03-10
約束過載
- 約束的定義：constraint name{},如果是想分佈的，用dist就可以。
- 約束的過載是把類繼承一下，被繼承瞭然後覆蓋約束，用子類完成功能呼叫。
module taa (); class con_base; rand int a; rand int b; constraint a_b{ a dist{0:=4, 1:= 1}; b dist{0:=2, 1:= 2}; } function void print(); $display("a is %d, b is %d", a, b); endfunction: print endclass class con_custom extends con_base; constraint a_b{ a ==1; b ==2; } function void print(); super.print(); endfunction: print endclass: con_custom initial begin con_base cons_inst = new(); con_custom cust_inst = new(); cust_inst.randomize(); cust_inst.print(); cust_inst.randomize(); cust_inst.print(); cust_inst.randomize(); cust_inst.print(); cust_inst.randomize(); cust_inst.print(); cust_inst.randomize(); cust_inst.print(); end endmodule
輸出結果：
a is 1, b is 2
a is 1, b is 2
a is 1, b is 2
a is 1, b is 2
a is 1, b is 2
工廠類的過載
- set_type_override等的方法，是繼承父類實現子類，然後過載最終以父類形式呼叫了子類。
- 一般的uvm方法是有virtual的，但是沒有就一定要加，都加也更保險一些，否則無法完成過載。
- set_type_override等的方法，需要在例項化以前被呼叫，才能實現過載功能，否則uvm_top.print_topology();看不到效果，雖然print_override_info可以看到效果。
module tbb (); import uvm_pkg::*; class source extends uvm_component; `uvm_component_utils(source) function new(string name="source", uvm_component parent); super.new(name, parent); endfunction: new virtual function void print(); `uvm_info("SOURCE", $sformatf("source print"), UVM_LOW) endfunction: print endclass: source class target extends source; `uvm_component_utils(target) function new(string name="target", uvm_component parent); super.new(name, parent); endfunction: new function void print(); `uvm_info("TARGET", $sformatf("target print"), UVM_LOW) endfunction: print endclass: target class my_test extends uvm_test; `uvm_component_utils(my_test) source s; target t; function new(string name="my_test", uvm_component parent); super.new(name, parent); endfunction: new function void build_phase(uvm_phase phase); super.build_phase(phase); set_type_override_by_type(source::get_type(), target::get_type()); s = source::type_id::create("s", this); t = target::type_id::create("t", this); uvm_top.print_topology(); print_override_info("source"); endfunction: build_phase function void start_of_simulation_phase(uvm_phase phase); super.start_of_simulation_phase(phase); s.print(); t.print(); endfunction:start_of_simulation_phase task run_phase(uvm_phase phase); s.print(); t.print(); endtask: run_phase endclass: my_test initial begin run_test("my_test"); end endmodule
輸出結果：
UVM_INFO @ 0: reporter [RNTST] Running test my_test...
UVM_INFO /home/synopsys/vcs-mx/O-2018.09-1/etc/uvm-1.2/base/uvm_root.svh(589) @ 0: reporter [UVMTOP] UVM testbench topology:
----------------------------------
Name Type Size Value
----------------------------------
uvm_test_top my_test - @335
s target - @348
t target - @357
----------------------------------
UVM_INFO /home/synopsys/vcs-mx/O-2018.09-1/etc/uvm-1.2/base/uvm_factory.svh(1786) @ 0: reporter [UVM/FACTORY/DUMP]
#### Factory Override Information (*)
Given a request for an object of type 'source' with an instance
path of 'uvm_test_top' the factory encountered
the following relevant overrides. An 'x' next to a match indicates a
match that was ignored.
Original Type Instance Path Override Type
------------- ------------- -------------
source
* target <type override>
Result:
The factory will produce an object of type 'target'
(*) Types with no associated type name will be printed as <unknown>
####
UVM_INFO tbb.sv(22) @ 0: uvm_test_top.s [TARGET] target print
UVM_INFO tbb.sv(22) @ 0: uvm_test_top.t [TARGET] target print
UVM_INFO tbb.sv(22) @ 0: uvm_test_top.s [TARGET] target print
UVM_INFO tbb.sv(22) @ 0: uvm_test_top.t [TARGET] target print
UVM_INFO /home/synopsys/vcs-mx/O-2018.09-1/etc/uvm-1.2/base/uvm_report_server.svh(894) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---
** Report counts by severity
UVM_INFO : 8
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[TARGET] 4
[UVM/FACTORY/DUMP] 1
[UVM/RELNOTES] 1
[UVMTOP] 1
$finish called from file "/home/synopsys/vcs-mx/O-2018.09-1/etc/uvm-1.2/base/uvm_root.svh", line 527.
$finish at simulation time 0
回撥函式
我這個只能在uvm1.1上用
開發者
- 定義A（回撥類），定義A_pool（回撥池）、定義元件如my_comp（呼叫回撥的元件）。
- 其中的A包括了回撥函式，A_pool中有元件和回撥類，元件中註冊了回撥類，然後使用uvm_do_callback巨集，完成回撥功能。
使用者 - 從回撥類A中繼承，定義子類，實現方法即可。使用者在使用元件的時候，順便例項化回撥的子類，加入到池子中（帶入元件和回撥類），就可以完成回撥的實現。
module tcc ();
import uvm_pkg::*;
typedef struct {
string a;
int b;
} my_trans;
typedef class my_comp;
class A extends uvm_callback;
`uvm_object_utils(A);
virtual task pre_trans(my_comp comp, ref my_trans tr);
endtask
endclass: A
typedef uvm_callbacks#(my_comp, A) A_pool;
class my_comp extends uvm_component;
`uvm_component_utils(my_comp)
`uvm_register_cb(my_comp, A)
function new(string name="my_comp", uvm_component parent);
super.new(name, parent);
endfunction: new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction: build_phase
task run_phase(uvm_phase phase);
my_trans tr= '{"hahaha", 345};
repeat (3) begin
`uvm_do_callbacks(my_comp, A, pre_trans(this, tr));
`uvm_info("COMP_TR", $sformatf("%s, %d", tr.a, tr.b), UVM_LOW)
end
endtask: run_phase
endclass: my_comp
//-------------------------------------------------------------------------------
class my_callback extends A;
`uvm_object_utils(my_callback)
task pre_trans(my_comp comp, ref my_trans tr);
tr.a = "123";
tr.b = 12;
`uvm_info("CB", $sformatf("callback is here."), UVM_LOW)
endtask: pre_trans
endclass: my_callback
class my_test extends uvm_test;
`uvm_component_utils(my_test)
my_callback my_cb;
my_comp comp;
function new(string name="my_test", uvm_component parent);
super.new(name, parent);
endfunction: new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
my_cb = my_callback::type_id::create("my_cb");
comp = my_comp::type_id::create("comp", this);
A_pool::add(comp, my_cb);
endfunction: build_phase
endclass: my_test
initial begin
run_test("my_test");
end
endmodule
輸出結果：
UVM_INFO @ 0: reporter [RNTST] Running test my_test...
UVM_INFO tcc.sv(44) @ 0: reporter [CB] callback is here.
UVM_INFO tcc.sv(31) @ 0: uvm_test_top.comp [COMP_TR] 123, 12
UVM_INFO tcc.sv(44) @ 0: reporter [CB] callback is here.
UVM_INFO tcc.sv(31) @ 0: uvm_test_top.comp [COMP_TR] 123, 12
UVM_INFO tcc.sv(44) @ 0: reporter [CB] callback is here.
UVM_INFO tcc.sv(31) @ 0: uvm_test_top.comp [COMP_TR] 123, 12
--- UVM Report Summary ---
** Report counts by severity
UVM_INFO : 7
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[CB] 3
[COMP_TR] 3
[RNTST] 1
$finish called from file "/home/synopsys/vcs-mx/O-2018.09-1/etc/uvm-1.1/base/uvm_root.svh", line 439.
$finish at simulation time 0