RFNoC完整開發流程記錄
阿新 • • 發佈：2022-04-01
1 前言
這篇文章以開發RFNoC-QPSK中的32bits-2bits轉換模組為例演示RFNoC的完整開發流程, 並且起名"Outline", 希望通過這一篇文章能夠快速回憶起流程. 因此這篇文章並不屬於任何章節而是獨立於書籍的根目錄的存在.
注: 目前採用X310平臺進行該流程
2 建立RFNoC Custom Module
這部分的詳情見RFNoC工具鏈簡介。
2.1 建立module
首先RFNoC module 是一個功能的工具集（類比gr-mod）。整個module包括多個blocks，共同組成某些功能的模組集合，我們首先就應該建立module。
➜ rfnocmodtool newmod --srcdir <UHD-Install-Prefix>/share/gr-ettus/rfnoc_modtool/rfnoc-newmod Name of the new module: qpsk Creating out-of-tree module in ./rfnoc-qpsk... Done. Use 'rfnocmodtool add' to add a new block to this currently empty module.
其中<UHD-Install-Prefix>是UHD的安裝路徑。
2.2 新增block
建立module之後，我們向其中新增第一個功能模組——32bits-2bits轉換。起名為conv32Bto2B，剩下的配置保持預設即可。
➜ cd rfnoc-qpsk ➜ rfnocmodtool add RFNoC module name identified: qpsk Enter name of block/code (without module name prefix): conv32Bto2B Block/code identifier: conv32Bto2B Enter valid argument list, including default arguments: Add Python QA code? [y/N] Add C++ QA code? [y/N] Block NoC ID (Hexadecimal): Random NoC ID generated: D6AA69D4 Skip Block Controllers Generation? [UHD block ctrl files] [y/N] Skip Block interface files Generation? [GRC block ctrl files] [y/N]
3 功能實現
本節內容是要完成新建立RFNoC的功能部分，主要的流程就是FPGA程式設計+仿真確認功能的正確性，在RFNoC 4.0中提供了完整的模擬庫，開發起來十分方便。
3.0 （更改NoC shell）
參考RFNoC CHDR 匯流排簡介，我們知道CHDR包括context和payload兩部分，如果是傳統一進一出的資料處理模式，則不需要改變context的內容，但是在32位資料轉2位資料的模式下，總線上的資料會變多。因此需要改變context的內容來告知CHDR資料變多（否則，CHDR只會讀出與你輸入數量相等的資料）。
而在CHDR資料轉換為更加容易處理的axis的資料，RFNoC提供了兩個（也許更多）的模組：chdr_to_axis_data
chdr_to_axis_pyld_ctxt。chdr_to_axis_pyld_ctxt直接將資料拆分為payload和context兩部分，如果你想單獨處理context的內容就需要進行手動的切片工作，對於不改變context內容的block，只需要將context的內容做透明轉發即可。chdr_to_axis_data會繼續把context上的內容繼續拆分為timestamp, has_time, length, eov, eob以及payload部分data。
因為我們需要更改context的內容以告知匯流排資料被本模組倍增了，因此需要將預設的noc_shell生成的chdr_to_axis_pyld_ctxt更改為chdr_to_axis_data。
更改只需要參考rfnoc_block_duc的noc_shell_duc即可，只是用chdr_to_axis_data替換了chdr_to_axis_pyld_ctxt。
3.1 新增資料處理模組
為了保證程式的結構清晰，強烈建議不要在生成的檔案中直接新增資料處理的程式碼，而是將資料處理單獨封裝成一個module，之後再在rfnoc_block_xxxx.v中例項化。
在本例中，我建立了QPSK_data_converter.v來實現資料的拆分轉換。則要注意：在rfnocmodtool生成的檔案之外建立的原始檔，需要手動新增到編譯目錄中，開啟rfnoc-<module name>/rfnoc/fpga/rfnoc_block_<block name>/Makefil.srcs，在RFNOC_OOT_SRCS中新增自定義檔案！！
# Makefile.srcs
# RFNoC Block Sources
# Here, list all the files that are necessary to synthesize this block. Don't
# include testbenches!
# Make sure that the source files are nicely detectable by a regex. Best to put
# one on each line.
# The first argument to addprefix is the current path to this Makefile, so the
# path list is always absolute, regardless of from where we're including or
# calling this file. RFNOC_OOT_SRCS needs to be a simply expanded variable
# (not a recursively expanded variable), and we take care of that in the build
# infrastructure.
RFNOC_OOT_SRCS += $(addprefix $(dir $(abspath $(lastword $(MAKEFILE_LIST)))), rfnoc_block_conv32Bto2B.v noc_shell_conv32Bto2B.v QPSK_data_converter.v)
3.2 模擬模組功能
建立好資料處理模組之後，最好對其進行模擬分析，因為X310編譯一次太久，提前完成資料分析有助於提前發現問題。
模擬的控制在rfnoc_block_<block name>_tb.sv檔案中定義。啟動模擬通過make rfnoc_block_<block name>_tb進行啟動。
# cmake生成makefile
cmake -DUHD_FPGA_DIR=<uhd-repo>/fpga -DCMAKE_INSTALL_PREFIX=/opt/gr38uhd4105 ..
# 啟動模擬
make rfnoc_block_conv32Bto2B_tb
如果想使用Qustasim進行更下細緻的模擬，可以參考RFNoC block 模擬方法
3.3 建立FPGA映象
makefile同樣提供了編譯FPGA映象的快捷指令
make <block name>_x319_rfnoc_image_core
注意：這裡有一個小bug，是yml檔案定義的版本號為float，而處理指令碼會將其當做string進行處理，因此需要手動將yml檔案中的rfnoc_version的欄位改為字串，報錯資訊如下：
File "/opt/gr38uhd4105/lib/python3.8/site-packages/uhd/imgbuilder/templates/rfnoc_image_core.vh.mako", line 3, in render_body
protover = config.rfnoc_version.split('.')
AttributeError: 'ScalarFloat' object has no attribute 'split'
修改的檔案包括
rfnoc/blocks/xxx.yml
rfnoc/icores/xxxx_x310_image_core.yml
4 安裝RFNoC custom module
為了能正確的在gnuradio中呼叫自定義的module，需要執行編譯安裝。
cd <rfnoc module dir>/build
make install
5 在GNU Radio中測試模組功能
可以使用自動生成的grc進行測試
在這裡對其稍微做出一點改動，框圖如下。
在執行gr之前，需要將編譯好的fpga映象寫入到x310中。
➜ uhd_image_loader --args="type=x300,addr=192.168.40.2" --fpga-path=<UHD-repo>/fpga/usrp3/top/x300/build-X310_HG/x300.bit
[INFO] [UHD] linux; GNU C++ version 9.3.0; Boost_107100; UHD_4.1.0.HEAD-0-g6bd0be9c
Unit: USRP X310 (31E24FC, 192.168.40.2)
FPGA Image: /home/lilacsat/Playground/rfnoc/src/uhd/fpga/usrp3/top/x300/build-X310_HG/x300.bit
-- Initializing FPGA loading...successful.
-- Loading FPGA image: 100% (121/121 sectors)
-- Finalizing image load...successful.
Power-cycle the USRP X310 to use the new image.
執行gr之前最好再用uhd_usrp_probe來確定映象已經被正確載入。
➜ uhd_usrp_probe --args "addr=192.168.40.2"
[INFO] [UHD] linux; GNU C++ version 9.3.0; Boost_107100; UHD_4.1.0.HEAD-0-g6bd0be9c
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 1472 bytes.
[WARNING] [X300] For the 192.168.40.2 connection, UHD recommends a send frame size of at least 8000 for best
performance, but your configuration will only allow 1472.This may negatively impact your maximum achievable sample rate.
Check the MTU on the interface and/or the send_frame_size argument.
[WARNING] [X300] For the 192.168.40.2 connection, UHD recommends a receive frame size of at least 8000 for best
performance, but your configuration will only allow 1472.This may negatively impact your maximum achievable sample rate.
Check the MTU on the interface and/or the recv_frame_size argument.
[INFO] [GPS] No GPSDO found
[INFO] [X300] Radio 1x clock: 200 MHz
[WARNING] [UDP] The recv buffer could not be resized sufficiently.
Target sock buff size: 24862979 bytes.
Actual sock buff size: 212992 bytes.
See the transport application notes on buffer resizing.
Please run: sudo sysctl -w net.core.rmem_max=24862979
[WARNING] [UDP] The send buffer could not be resized sufficiently.
Target sock buff size: 24862979 bytes.
Actual sock buff size: 212992 bytes.
See the transport application notes on buffer resizing.
Please run: sudo sysctl -w net.core.wmem_max=24862979
[WARNING] [UDP] The current recv_buff_size of 212992 is less than the minimum recommended size of 816000 and may result in dropped packets on some NICs
[WARNING] [UDP] The current send_buff_size of 212992 is less than the minimum recommended size of 307200 and may result in dropped packets on some NICs
[WARNING] [RFNOC::BLOCK_FACTORY] Could not find block with Noc-ID 0xd6aa69d4, 0xffff
_____________________________________________________
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X310
| | revision: 11
| | revision_compat: 7
| | product: 30818
| | mac-addr0: 00:80:2f:30:ed:c5
| | mac-addr1: 00:80:2f:30:ed:c6
| | gateway: 192.168.10.1
| | ip-addr0: 192.168.10.2
| | subnet0: 255.255.255.0
| | ip-addr1: 192.168.20.2
| | subnet1: 255.255.255.0
| | ip-addr2: 192.168.30.2
| | subnet2: 255.255.255.0
| | ip-addr3: 192.168.40.2
| | subnet3: 255.255.255.0
| | serial: 31E24FC
| | FW Version: 6.0
| | FPGA Version: 38.0
| | FPGA git hash: 6bd0be9
| |
| | Time sources: internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| _____________________________________________________
| /
| | RFNoC blocks on this device:
| |
| | * 0/Block#0
| | * 0/DDC#0
| | * 0/DDC#1
| | * 0/DUC#0
| | * 0/DUC#1
| | * 0/Radio#0
| | * 0/Radio#1
| _____________________________________________________
| /
| | Static connections on this device:
| |
| | * 0/SEP#0:0==>0/DUC#0:0
| | * 0/DUC#0:0==>0/Radio#0:0
| | * 0/Radio#0:0==>0/DDC#0:0
| | * 0/DDC#0:0==>0/SEP#0:0
| | * 0/Radio#0:1==>0/DDC#0:1
| | * 0/DDC#0:1==>0/SEP#1:0
| | * 0/SEP#2:0==>0/DUC#1:0
| | * 0/DUC#1:0==>0/Radio#1:0
| | * 0/Radio#1:0==>0/DDC#1:0
| | * 0/DDC#1:0==>0/SEP#2:0
| | * 0/Radio#1:1==>0/DDC#1:1
| | * 0/DDC#1:1==>0/SEP#3:0
| | * 0/SEP#4:0==>0/Block#0:0
| | * 0/Block#0:0==>0/SEP#4:0
| _____________________________________________________
| /
| | TX Dboard: 0/Radio#0
| | ID: UBX-160 v2 (0x007d)
| | Serial: 31DE8D1
| | _____________________________________________________
| | /
| | | TX Frontend: 0
| | | Name: UBX TX
| | | Antennas: TX/RX, CAL
| | | Sensors: lo_locked
| | | Freq range: 10.000 to 6000.000 MHz
| | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | Connection Type: QI
| | | Uses LO offset: No
| _____________________________________________________
| /
| | RX Dboard: 0/Radio#0
| | ID: UBX-160 v2 (0x007e)
| | Serial: 31DE8D1
| | _____________________________________________________
| | /
| | | RX Frontend: 0
| | | Name: UBX RX
| | | Antennas: TX/RX, RX2, CAL
| | | Sensors: lo_locked
| | | Freq range: 10.000 to 6000.000 MHz
| | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | Connection Type: IQ
| | | Uses LO offset: No
| _____________________________________________________
| /
| | TX Dboard: 0/Radio#1
| | ID: Unknown (0x0094)
| | Serial: 3188C83
| | _____________________________________________________
| | /
| | | TX Frontend: 0
| | | Name: Unknown (0x0094) - 0
| | | Antennas:
| | | Sensors:
| | | Freq range: 0.000 to 0.000 MHz
| | | Gain Elements: None
| | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz
| | | Connection Type: IQ
| | | Uses LO offset: No
| _____________________________________________________
| /
| | RX Dboard: 0/Radio#1
| | ID: TwinRX Rev C (0x0095)
| | Serial: 3190DF9
| | _____________________________________________________
| | /
| | | RX Frontend: 0
| | | Name: TwinRX RX0
| | | Antennas: RX1, RX2
| | | Sensors: lo_locked
| | | Freq range: 10.000 to 6000.000 MHz
| | | Gain range all: 0.0 to 93.0 step 1.0 dB
| | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
| | | Connection Type: II
| | | Uses LO offset: No
| | _____________________________________________________
| | /
| | | RX Frontend: 1
| | | Name: TwinRX RX1
| | | Antennas: RX1, RX2
| | | Sensors: lo_locked
| | | Freq range: 10.000 to 6000.000 MHz
| | | Gain range all: 0.0 to 93.0 step 1.0 dB
| | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
| | | Connection Type: QQ
| | | Uses LO offset: No
測試結果
因為沒有做幅值對映，只是將資料拆解開，放到最低兩位，所以資料有4種情況。圖中可見四種幅值的資料點。
回到目錄