參考網址：https://blog.csdn.net/weixin_43506155/article/details/118179930?spm=1001.2101.3001.6661.1&utm_medium=distribute.pc_relevant_t0.none-task-blog-2~default~CTRLIST~Rate-1.pc_relevant_default&depth_1-utm_source=distribute.pc_relevant_t0.none-task-blog-2~default~CTRLIST~Rate-1.pc_relevant_default&utm_relevant_index=1

程式碼：

module led0_module(CLK, RSTn, LED_out);
    input CLK;
    input RSTn;
    output LED_out;
    
    /********************************/
    parameter T1S = 26'd50;
    /********************************/
    
    reg [25:0] Count1;
    
    always @(posedge CLK or negedge RSTn)
        if(!RSTn)
            Count1 
 
<= 26'd0;
        else if(Count1 == T1S)
            Count1 <= 26'd0;
        else
            Count1 <= Count1 + 1'b1;
            
    /********************************/
    
    reg rLED_out;
    always @(posedge CLK or negedge RSTn)
        if(!RSTn)
            rLED_out <= 1'b0;
        else
 
 if(Count1 >= 26'd0 && Count1 < 26'd25)
            rLED_out <= 1'b1;
        else
            rLED_out <= 1'b0;
            
    /********************************/
    
    assign LED_out = rLED_out;
    
    /********************************/
    
endmodule

led0_tb.vb

`timescale 1 ns/ 1 ns//模擬的單位時間為1ns， 精度為1ps
module led0_tb;
    reg clk;
    reg rstn;
    wire led0_out;
    initial
    begin
        rstn = 0;
        #10 rstn = 1;
        clk = 0;
        frever #1 clk = ~clk;
    end
    
led0_module U1(
    .CLK(clk), 
    .RSTn(rstn), 
    .LED_out(led0_out)
);

endmodule