基於FPGA的均值濾波（四）

之除法電路模組

假定求和結果為sum，計算後的均值為Average，則有

可以通過上式的計算誤差為：

以5x5的視窗為例，將除法電路加上後得到的求均值電路如下圖所示：

reg [2*DW-1:0] mean_temp;
reg [2*DW-1:0] mean_temp1;
reg [2*DW-1:0] mean_temp2;
reg [2*DW-1:0] mean_temp3;
reg [2*DW-1:0] mean_temp4;
reg [2*DW-1:0] mean_temp5;
reg [2*DW-1:0] mean_temp6;
reg [2*DW-1:0] mean_temp7;
reg [2*DW-1:0] mean_temp8;
wire [DW-1:0] mean_temp9;
wire [DW+3-1:0] mean_temp10;
wire [2*DW+6-1:0] mean_temp11;
wire [2*DW-1:0] mean_out_temp;
generate
if(KSZ==5)
begin : divide_25
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
mean_temp <= {2*DW-1+1{1'b0}};
mean_temp1 <= {2*DW-1+1{1'b0}};
mean_temp2 <= {2*DW+1{1'b0}};
mean_temp3 <= {2*DW+5-1+1{1'b0}};
mean_temp4 <= {2*DW+6-1+1{1'b0}};
mean_temp5 <= {2*DW+1-1+1{1'b0}};
mean_temp6 <= {2*DW+6-1+1{1'b0}};
end
else
begin
//將二維求和結果快取到mean_temp
if(sum_dout_valid[3])
mean_temp <= sum_dout_r[2];
//下一拍計算
if(sum_dout_valid[4])
begin
//計算mean_temp (2^-6+2^-7)
mean_temp1 <= ({6'b000000,mean_temp[2*DW-1:6]})+({7'b0000000,mean_temp[2*DW-1:7]});
//計算mean_temp (2^-3+2^-4)
mean_temp2 <= ({4'b0000,mean_temp[2*DW-1:4]})+({5'b00000,mean_temp[2*DW-1:5]});
//計算mean_temp (2^-1+2^-2)
mean_temp3 <= ({1'b0,mean_temp[2*DW-1:1]})+({2'b00,mean_temp[2*DW-1:2]});
//計算mean_temp (2^3+2^5)
mean_temp4 <= ({mean_temp[2*DW-4:0]},3'b000)+({mean_temp[2*DW-6:0]},5'b00000);
end
//下一排計算上一排的中間結果
if(sum_dout_valid[5])
begin
mean_temp5 <= mean_temp1 + mean_temp2;
mean_temp6 <= mean_temp3 + mean_temp4;
end
//下一排計算上一排的中間結果
if(sum_dout_valid[6])
mean_temp7<= mean_temp6 + mean_temp7;
end
end
endgenerate
//求和結果除以1024的結果
assign mean_temp8 = (sum_is_broarder_r[6]==1'b0)?(mean_temp7>>10):(2*DW{1'b0});
//四捨五入操作
assign mean_temp9 = (mean_temp[7] == 1'b1) ? (mean_temp8[DW-1:0]+1'b1):mean_temp8[DW-1:0];
//對輸出結果儲存三位小數‘
assign mean_temp11 = (sum_is_broarder_r[6]==1'b0) ? (mean_temp7>>7) : {2*DW-1-1{1'b0}};
assign mean_temp10 = (mean_temp11[DW+3-1:0] + 1'b1)