狀態轉換圖：

module det(
input clk,
input rst_n,
input d,  //資料輸入
output reg y   //檢測結果輸出
);
/*
 檢測101101
*/
//狀態編碼
parameter idle=3'b000; //空閒狀態
parameter s1=3'b001;   //檢測到1
parameter s2=3'b010;   //檢測到10
parameter s3=3'b011;   //檢測到101
parameter s4=3'b100;   //檢測到1011
parameter s5=3'b101;   //檢測到10110
parameter s6=3'b110;   //檢測到101101

reg[2
 
:0]cur_state,nxt_state;
always@(posedge clk or negedge rst_n)
if(!rst_n)
 cur_state<=idle;
else 
 cur_state<=nxt_state; 

always@(cur_state,d)
begin
case(cur_state)
idle:
begin
 if(d==1'b1)
  nxt_state<=s1;
 else 
  nxt_state<=idle;
end 
s1:
begin
 if(d==1'b0)
  nxt_state<=s2;
 else 
  nxt_state
 
<=idle;
end 
s2:
begin
 if(d==1'b1)
  nxt_state<=s3;
 else 
  nxt_state<=idle;
end 
s3:
begin
 if(d==1'b1)
  nxt_state<=s4;
 else 
  nxt_state<=idle;
end 
s4:
begin
 if(d==1'b0)
  nxt_state<=s5;
 else 
  nxt_state<=idle;
end 
s5:
begin
 if(d==1'b1)
  nxt_state<=s6;
 else 
  nxt_state
 
<=idle;
end 
s6:
begin
 if(d==1'b1)
  nxt_state<=s1;
 else 
  nxt_state<=idle;
end 
default:;
endcase  
end 

always@(posedge clk or negedge rst_n)
if(~rst_n)
 y<=1'b0;
else if(nxt_state==s6)
 y<=1'b1;
else 
 y<=1'b0;
endmodule