[dpdk] TSC ， HPET， Timer， Event Timer，RDTSCP
關於dpdk timer跨越CPU core調度的準確性問題
首先dpdk的timer接口裏邊使用 cpu cycle來比較時間。根據之前的內容
[dpdk] dpdk --lcores參數
當一個EAL thread映射在多個processor上的時候，cpu cycle有可能在不同的CPU core上面獲得，
又因為cpu cycle是使用rdtsc指令獲取的，這樣會造成拿到的cpu cycle不準的問題。
首先，調查一下 rdtsc 指令：
https://stackoverflow.com/questions/3388134/rdtsc-accuracy-across-cpu-cores?utm_medium=organic&utm_source=google_rich_qa&utm_campaign=google_rich_qa
Invariant TSC
X86_FEATURE_CONSTANT_TSC + X86_FEATURE_NONSTOP_TSC
"16.11.1 Invariant TSC The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. Processor‘s support for
invariant TSC is indicated by CPUID.80000007H:EDX[8]. The invariant TSC will run at a constant ratein all ACPI P-, C-. and T-states. This is the architectural behavior moving
forward. On processors with invariant TSC support, the OS may use the TSC for wall clock timer services (instead of ACPI or
HPET timers). TSC reads are much more efficient and do not incur the overhead associated with a ring transition or
access to a platform resource."
[root@D128 ~]# cat /proc/cpuinfo |grep tsc constant_tsc nonstop_tsc
只能保證在單個core 改變頻率或掛起的時候的tsc準確性，不能保證跨CPU core的同步問題。
https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/388964
Hello Samuel, The ‘Invariant TSC‘ means that the TSC runs at a fixed frequency and doesn‘t stop when the cpu halts. The TSCs are not guaranteed to be synchronized although the OS usually does try to synchronize the TSC at boot time. This is one reason
for the rdtscp instruction. On Nehalem and later cpus, the rdtscp instruction returns the TSC and an identifier indicating on which cpu
you read the TSC. RDTSCP is a serializing instruction... unlike the regular rdtsc instruction. Pat
HPET
https://en.wikipedia.org/wiki/High_Precision_Event_Timer
An HPET chip consists of a 64-bit up-counter (main counter) counting at a frequency of at least 10 MHz,
and a set of (at least three, up to 256) comparators. These comparators are 32- or 64-bit-wide. The HPET
is programmed via a memory mapped I/O window that is discoverable via Advanced Configuration and Power
Interface (ACPI). The HPET circuit in modern PCs is integrated into the southbridge chip.[a]
HPET是一個芯片全局的計數器，最小精度為10納秒，一般集成在南橋。
HPET提供最少3最多256個獨立的計數器。
The Linux kernel can also use HPET as its clock source. The documentation of Red Hat MRG version 2 states that TSC is the preferred
clock source due to its much lower overhead, but it uses HPET as a fallback. A benchmark in that environment for 10 million event
counts found that TSC took about 0.6 seconds, HPET took slightly over 12 seconds, and ACPI Power Management Timer took around 24 seconds.[5]
雖然精度高，到底有性能損耗，linux Kernel仍然推薦TSC作為首選計數器，HPET作為備選。
查看HPET是否啟用：
[root@D129 cli]# grep hpet /proc/timer_list Clock Event Device: hpet set_next_event: hpet_legacy_next_event set_mode: hpet_legacy_set_mode [root@D129 jstack-vrouter]# cat /sys/devices/system/clocksource/clocksource0/available_clocksource kvm-clock hpet acpi_pm [root@D129 jstack-vrouter]# cat /sys/devices/system/clocksource/clocksource0/current_clocksource kvm-clock [root@D129 jstack-vrouter]# ll /dev/hpet crw-------. 1 root root 10, 228 May 3 16:23 /dev/hpet [root@D129 jstack-vrouter]#
dpdk如何配置生效:
https://dpdk.org/doc/guides/linux_gsg/enable_func.html#high-precision-event-timer-hpet-functionality
rdtscp
ACPI
略。
Event Timer Adapter Library
https://dpdk.org/doc/guides/prog_guide/event_timer_adapter.html#id1
看完以上文檔，讀一下代碼，確定兩個問題：
1. RDTSC的調用時機
2. Event Timer backend的hardware是什麽？
其他參考閱讀：
https://www.ibm.com/developerworks/cn/linux/l-cn-timerm/
[dpdk] TSC ， HPET， Timer， Event Timer，RDTSCP