kernel/arch/arm/mach-rockchip/rk_fiq_debugger.c

搜尋：static int debug_port_init(struct platform_device *pdev)
將該函式內容替換為以下即可：
int dll = 0, dlm = 0;
    struct rk_fiq_debugger *t;

    t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);

    if (rk_fiq_read(t, UART_LSR) & UART_LSR_DR)
        (void)rk_fiq_read(t, UART_RX);

    //switch (t->baudrate) {
    //case 1500000:
        //dll = 0x1;
        //break;
    //case 115200:
    //default:
        dll = 0xd;
        //break;
    //}

    rk_fiq_write(t, 0x83, UART_LCR);
    /* set baud rate */
    rk_fiq_write(t, dll, UART_DLL);
    rk_fiq_write(t, dlm, UART_DLM);
    rk_fiq_write(t, 0x03, UART_LCR);

    /* enable rx and lsr interrupt */
    rk_fiq_write(t, UART_IER_RLSI | UART_IER_RDI, UART_IER);
    /* interrupt on every character when receive,but we can enable fifo for TX
    I found that if we enable the RX fifo, some problem may vanish such as when
    you continuously input characters in the command line the uart irq may be disable
    because of the uart irq is served when CPU is at IRQ exception,but it is
    found unregistered, so it is disable.
    

    return 0;

rk3288.dtsi裡fiq_debugger改成以下：
fiq_debugger: fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <3>;
rockchip,signal-irq = <182>;      //無論是哪一個口，都不用修改該數值
rockchip,wake-irq = <0>;
rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
rockchip,baudrate = <1500000>; / *Only 115200 and 1500000 */
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
};

rk3288-popmetal.dts裡需要新增:
&uart_gps{
status = "okay";
dma-names = "!tx", "!rx";
pinctrl-0 = <&uart3_xfer &uart3_cts>; 
};
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作者：困於往事 
來源：CSDN 
原文：https://blog.csdn.net/HWQ331717300/article/details/72275982?utm_source=copy 
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