Verilog 常見警告/錯誤彙總
Verilog 常見錯誤彙總
1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"
原因:vector source file中時鐘敏感訊號(如:資料,允許端,清零,同步載入等)在時鐘的邊緣同時變化.而時鐘敏感訊號是不能在時鐘邊沿變化的.其後果為導致結果不正確.
措施:編輯vector source file
2.Verilog HDL assignment warning at <location>: truncated with size <number> to match size of target (<number>
原因:在HDL設計中對目標的位數進行了設定,如:reg[4:0] a;而預設為32位, 將位數裁定到合適的大小
措施:如果結果正確,無須加以修正,如果不想看到這個警告,可以改變設定的位數
3.All reachable assignments to data_out(10) assign '0', register removed by optimization
原因:經過綜合器優化後,輸出埠已經不起作用了
4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
原因:有9個腳為空或接地或接上了電源
措施:有時候定義了輸出埠,但輸出端直接賦‘0’,便會被接地,賦‘1’接電源. 如果你的設計中這些埠就是這樣用的,那便可以不理會這些warning
5.Found pins functioning as undefined clocks and/or memory enables
原因:是你作為時鐘的PIN沒有約束資訊.可以對相應的PIN做一下設定就行了. 主要是指你的某些管腳在電路當中起到了時鐘管腳的作用,比如flip-flop的clk 管腳,而此管腳沒有時鐘約束,因此QuartusII把“clk”作為未定義的時鐘.
措施:如果clk不是時鐘,可以加“not clock”的約束;如果是,可以在clock setting當中加入;在某些對時鐘要求不很高的情況下,可以忽略此警告或在這裡修改:Assignments>Timing analysis settings...>Individual
clocks...>...
6.Timing characteristics of device EPM570T144C5 are preliminary
原因:因為MAXII 是比較新的元件在 QuartusII 中的時序並不是正式版的,要等 Service Pack
措施:隻影響 Quartus 的 Waveform
7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
措施:將setting中的timing Requirements&Option-->More Timing Setting-->setting-->Enable Clock Latency中的on改成OFF
8.Found clock high time violation at 14.8 ns on register "|counter|lpm_counter:count1_rtl_0|dffs[11]"
原因:違反了steup/hold時間,應該是後模擬,看看波形設定是否和時鐘沿符合steup/hold時間
措施:在中間加個暫存器可能可以解決問題
9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay
原因:時鐘抖動大於資料延時,當時鍾很快,而if等類的層次過多就會出現這種問 題,但這個問題多是在器件的最高頻率中才會出現
措施:setting-->timing Requirements&Options-->Default required fmax 改小一些,如改到50MHZ
10.Design contains <number> input pin(s) that do not drive logic
原因:輸入引腳沒有驅動邏輯(驅動其他引腳),所有的輸入引腳需要有輸入邏輯
措施:如果這種情況是故意的,無須理會,如果非故意,輸入邏輯驅動.
11.Warning:Found clock high time violation at 8.9ns on node 'TEST3.CLK'
原因:FF中輸入的PLS的保持時間過短
措施:在FF中設定較高的時鐘頻率
12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
原因:如果你用的 CPLD 只有一組全域性時鐘時,用全域性時鐘分頻產生的另一個時 鍾在佈線中當作訊號處理,不能保證低的時鐘歪斜(SKEW).會造成在這個時鐘 上工作的時序電路不可靠,甚至每次佈線產生的問題都不一樣.
措施:如果用有兩組以上全域性時鐘的 FPGA 晶片,可以把第二個全域性時鐘作為另 一個時鐘用,可以解決這個問題.
13.Critical Warning: Timing requirements were not met. See Report window for details.
原因:時序要求未滿足,
措施:雙擊Compilation Report-->Time Analyzer-->紅色部分(如clock setup:'clk'等)-->左鍵單擊list path,檢視fmax的SLACK REPORT再根據 提示解決,有可能是程式的演算法問題
14.Can't achieve minimum setup and hold requirement <text> along <number> path(s). See Report window for details.
原因:時序分析發現一定數量的路徑違背了最小的建立和保持時間,與時鐘歪斜 有關,一般是由於多時鐘引起的
措施:利用Compilation Report-->Time Analyzer-->紅色部分(如clock hold:'clk'等),在slack中觀察是hold time為負值還是setup time 為負值, 然後在:Assignment-->Assignment Editor-->To中增加時鐘名(from
node finder),Assignment Name中增加 和多時鐘有關的Multicycle 和Multicycle Hold選項,如hold time為負,可 使Multicycle hold的值>multicycle,如設為2和1.
15: Can't analyze file -- file E://quartusii/*/*.v is missing
原因:試圖編譯一個不存在的檔案,該檔案可能被改名或者刪除了
措施:不管他,沒什麼影響
16.Warning: Can't find signal in vector source file for input pin |whole|clk10m
原因:因為你的波形模擬檔案( vector source file )中並沒有把所有的輸入 訊號(input pin)加進去,對於每一個輸入都需要有激勵源的
17.Error: Can't name logic scfifo0 of instance "inst" -- has same name as current design file
原因:模組的名字和project的名字重名了
措施:把兩個名字之一改一下,一般改模組的名字
18.Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0
原因:模組不是在本專案生成的,而是直接copy了別的專案的原理圖和源程式 而生成的,而不是用QUARTUS將檔案新增進本專案
措施:無須理會,不影響使用
19.Timing characteristics of device <name> are preliminary
原因:目前版本的QuartusII只對該器件提供初步的時序特徵分析
措施:如果堅持用目前的器件,無須理會該警告.關於進一步的時序特徵分析會在後續版本的Quartus得到完善.
20.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
原因:用analyze_latches_as_synchronous_elements setting可以讓 Quaruts II來分析同步鎖存,但目前的器件不支援這個特性
措施:無須理會.時序分析可能將鎖存器分析成迴路.但並不一定分析正確.其 後果可能會導致顯示提醒使用者:改變設計來消除鎖 存器
21.Warning:Found xx output pins without output pin load capacitance assignment
原因:沒有給輸出管教指定負載電容
措施:該功能用於估算TCO和功耗,可以不理會,也可以在Assignment Editor 中為相應的輸出管腳指定負載電容,以消除警告
22.Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
原因:使用了行波時鐘或門控時鐘,把觸發器的輸出當時鍾用就會報行波時鐘, 將組合邏輯的輸出當時鍾用就會報門控時鐘
措施:不要把觸發器的輸出當時鍾,不要將組合邏輯的輸出當時鍾,如果本身如 此設計,則無須理會該警告
23.Warning (10268): Verilog HDL information at lcd7106.v(63): Always Construct contains both blocking and non-blocking assignments
原因: 一個always模組中同時有阻塞和非阻塞的賦值
24.Warning: Can't find signal in vector source file for input pin |whole|clk10m
原因：這個時因為你的波形模擬檔案（ vector source file ）中並沒有把所有的輸入訊號(input pin)加進去， 對於每一個輸入都需要有激勵源的
25 Warning:Output pins are stuck at VCC or GND
如果正是希望某些輸出被固定置高電平或低電平或者無所謂，就不用管它，否則請檢查程式碼。這樣的輸出其實沒有什麼意義.
26.Warning (10208): honored full_case synthesis attribute - differences between design synthesis and simulation may occur。
/* synopsys full_case */;
意思就是：,告訴合成軟體你的case幾乎是full case，你（designer）可以保證沒有列出的case分支是永遠也不會發生的。 {
目的：告訴合成軟體不用去考慮沒有列出的case分支，便於化簡。
限制：當然只有synopsys 的合成軟體可以看懂了！所以不建議用，最好還是用default。
缺點：前後模擬不一致，綜合的結果和期望的不一致。
27：Warning: No exact pin location assignment(s) for 16 pins of 16 total pins
定義的管腳沒有和外部的管腳連線.
28：Warning: Ignored locations or region assignments to the following nodes
Warning: Node "78ledcom[4]" is assigned to location or region, but does not exist in design
設計中沒提到"78ledcom[4]" ，而分配了管腳給它。
說明：有時候運行了TCL指令碼檔案後需要修改，修改後有一些先前分配的管腳不需要了，如果沒有delete，則會出現此提示。
解決辦法：assignments->pins，把不用的管腳刪除即可（TCL指令碼檔案裡的多餘管腳分配語句最好也一起delete）。
1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list
----沒把singal放到process（）中
2 Warning: Found pins ing as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
-=-----可能是說設計中產生的觸發器沒有使能端
3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.
------訊號型別設定不對，out當作buffer來定義
4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"
-------引用的例化元件未定義實體－－entity "clk_gen"
5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer
Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer
6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.
7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
-----缺少敏感訊號
8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register
9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND
10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details.
11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details.
12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out"
------兩者不能連線起來
13 Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in design.
------沒有編寫testbench檔案，或者沒有編輯輸入變數的值 testbench裡是元件申明和對映
14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component
---在相關的元件裡沒有當前檔案所定義的型別
15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because signal does not hold its outside clock edge
16 Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]"
17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source file node.
---"temp[19]"被優化掉了
18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND
19 Warning: Design contains 2 input pin(s) that do not drive logic
Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "sign"
------輸出訊號與輸入訊號無關，
20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"
21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or"
22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared
-------連線表錯誤，形參"alarm"賦值給實參，形參沒定義，可能是形參與實參的位置顛倒了，規定形參在實參之前。
23 Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors
－－－－－－－－因為前一個錯誤而導致的錯誤
24 Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does not agree with its usage as std_logic type
－－－－－－－－"alarm"的定義型別與使用的型別不一致
25 Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that test for the edges of multiple clocks
-------同一程序中含有兩個或多個if(edge)條件，（一個程序中之能有一個時鐘沿）
26 Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at shift_reg.vhd(19)
27 can't infer register for signal "num[0]" because signal does not hold its outside clock edge
28 Error: Can't elaborate top-level user hierarchy
29 Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32) ----------有兩個以上賦值語句，不能確定“cs_in”的值
30 Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design.
---------------在原始檔中找不到對應的節點“over”。
31 Error: Can't access JTAG chain
無法找到下載鏈
1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"
原因：vector source file中時鐘敏感訊號（如：資料，允許端，清零，同步載入等）在時鐘的邊緣同時變化。而時鐘敏感訊號是 不能在時鐘邊沿變化的。其後果為導致結果不正確。
措施：編輯vector source file
2.Verilog HDL assignment warning at <location>: truncated value with size <number> to match size of target (<number>
原因:在HDL設計中對目標的位數進行了設定,如:reg[4:0] a;而預設為32位,將位數裁定到合適的大小 措施:如果結果正確,無須加以修正,如果不想看到這個警告,可以改變設定的位數
3.All reachable assignments to data_out(10) assign '0', register removed by optimization 原因:經過綜合器優化後，輸出埠已經不起作用了
4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
原因:第9腳，空或接地或接上了電源 措施:有時候定義了輸出埠，但輸出端直接賦‘0’，便會被接地，賦‘1’接電源。如果你的設計中這些埠就是這樣用的，那便可以不理會這些warning
5.Found pins functioning as undefined clocks and/or memory enables
原因:是你作為時鐘的PIN沒有約束資訊。可以對相應的PIN做一下設定就行了。主要是指你的某些管腳在電路當中起到了時鐘管腳的 作用，比如flip-flop的clk管腳，而此管腳沒有時鐘約束，因此QuartusII把“clk”作為未定義的時鐘。
措施:如果clk不是時鐘，可以加“not clock”的約束；如果是，可以在clock setting當中加入；在某些對時鐘要求不很高的情況下，可以忽略此警告或在這裡修改:Assignments>Timing analysis settings...>Individual clocks...>... 注意在Applies to node中只用選擇時鐘引腳一項即可，required fmax一般比所要求頻率高5%即可，無須太緊或太鬆。
6.Timing characteristics of device EPM570T144C5 are preliminary
原因:因為MAXII 是比較新的元件在 QuartusII 中的時序並不是正式版的,要等 Service Pack 措施:隻影響 Quartus 的 Waveform
7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
措施:將setting中的timing Requirements&Option-->More Timing Setting-->setting-->Enable Clock Latency中的on改成OFF
8.Found clock high time violation at 14.8 ns on register "|counter|lpm_counter:count1_rtl_0|dffs[11]"
原因:違反了steup/hold時間，應該是後模擬，看看波形設定是否和時鐘沿符合steup/hold時間
措施:在中間加個暫存器可能可以解決問題
9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay
原因:時鐘抖動大於資料延時,當時鍾很快，而if等類的層次過多就會出現這種問題,但這個問題多是在器件的最高頻率中才會出現
措施：setting-->timing Requirements&Options-->Default required fmax 改小一些，如改到50MHZ
10.Design contains <number> input pin(s) that do not drive logic
原因:輸入引腳沒有驅動邏輯(驅動其他引腳）,所有的輸入引腳需要有輸入邏輯
措施:如果這種情況是故意的,無須理會,如果非故意,輸入邏輯驅動.
11.Warning：Found clock high time violation at 8.9ns on node 'TEST3.CLK'
原因：FF中輸入的PLS的保持時間過短
措施：在FF中設定較高的時鐘頻率
12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
原因:如果你用的 CPLD 只有一組全域性時鐘時，用全域性時鐘分頻產生的另一個時鐘在佈線中當作訊號處理，不能保證低的時鐘歪斜(SKEW)。會造成在這個時鐘上工作的時序電路不可靠，甚至每次佈線產生的問題都不一樣。
措施:如果用有兩組以上全域性時鐘的 FPGA 晶片，可以把第二個全域性時鐘作為另一個時鐘用，可以解決這個問題。
13.Critical Warning: Timing requirements were not met. See Report window for details.
原因：時序要求未滿足，
措施：雙擊Compilation Report-->Time Analyzer-->紅色部分（如clock setup:'clk'等）-->左鍵單擊list path,檢視fmax的SLACK REPORT再根據提示解決,有可能是程式的演算法問題或fmax設定問題
14.Warning: Can't find signal in vector source file for input pin |whole|clk10m
原因：這個時因為你的波形模擬檔案（ vector source file ）中並沒有把所有的輸入訊號(input pin)加進去，對於每一個輸入都需要有激勵源的
15.Can't achieve minimum setup and hold requirement <text> along <number> path(s). See Report window for details.
原因：時序分析發現一定數量的路徑違背了最小的建立和保持時間，與時鐘歪斜有關,一般是由於多時鐘引起的
措施：利用Compilation Report-->Time Analyzer-->紅色部分（如clock hold:'clk'等），在slack中觀察是hold time為負值還是setup time 為負值，然後在：Assignment-->Assignment Editor-->To中增加時鐘名(from node finder)，Assignment Name中增加和多時鐘有關的Multicycle 和Multicycle Hold選項，如hold time為負，可使Multicycle hold的值>multicycle,如設為2和1。
16: Can't analyze file -- file E://quartusii/*/*.v is missing
原因：試圖編譯一個不存在的檔案，該檔案可能被改名或者刪除了
措施：不管他，沒什麼影響
17.Warning: Can't find signal in vector source file for input pin |whole|clk10m
原因：因為你的波形模擬檔案（ vector source file ）中並沒有把所有的輸入訊號(input pin)加進去，對於每一個輸入都需要有激勵源的
18.Error: Can't name logic function scfifo0 of instance "inst" -- function has same name as current design file
原因：模組的名字和project的名字重名了
措施：把兩個名字之一改一下，一般改模組的名字
19.Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0
原因：模組不是在本專案生成的，而是直接copy了別的專案的原理圖和源程式而生成的，而不是用QUARTUS將檔案新增進本專案
措施：無須理會，不影響使用
20.Timing characteristics of device <name> are preliminary
原因：目前版本的QuartusII只對該器件提供初步的時序特徵分析
措施：如果堅持用目前的器件，無須理會該警告。關於進一步的時序特徵分析會在後續版本的Quartus得到完善。
21.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
原因：用analyze_latches_as_synchronous_elements setting可以讓Quaruts II來分析同步鎖存，但目前的器件不支援這個特性
措施：無須理會。時序分析可能將鎖存器分析成迴路。但並不一定分析正確。其後果可能會導致顯示提醒使用者：改變設計來消除鎖存器,但實際其實無關緊要
22.Warning:Found xx output pins without output pin load capacitance assignment
原因：沒有給輸出管教指定負載電容
解決方法：該功能用於估算TCO和功耗，可以不理會，也可以在Assignment Editor中為相應的輸出管腳指定負載電容，以消除警告
Quartus常見錯誤分析 Error
1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list
----沒把singal放到process（）中
2 Warning: Found pins ing as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock
-=-----可能是說設計中產生的觸發器沒有使能端
3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout.
------訊號型別設定不對，out當作buffer來定義
4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen"
-------引用的例化元件未定義實體－－entity "clk_gen"
5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer
Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer
6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.
7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
-----缺少敏感訊號
8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register
9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND
10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details.
11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details.
12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out"
------兩者不能連線起來
13 Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in design.
------沒有編寫testbench檔案，或者沒有編輯輸入變數的值 testbench裡是元件申明和對映
14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component
---在相關的元件裡沒有當前檔案所定義的型別
15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because signal does not hold its outside clock edge
16 Warning: Found clock high time violation at 1000.0 ns on register
"|fcounter|lpm_counter:temp_rtl_0|dffs[4]"
17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source file node.
---"temp[19]"被優化掉了
18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND
19 Warning: Design contains 2 input pin(s) that do not drive logic
Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "sign"
------輸出訊號與輸入訊號無關，
20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"
21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or"
22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared
-------連線表錯誤，形參"alarm"賦值給實參，形參沒定義，可能是形參與實參的位置顛倒了，規定形參在實參之前。
23 Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors
－－－－－－－－因為前一個錯誤而導致的錯誤
24 Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does not agree with its usage as std_logic type
－－－－－－－－"alarm"的定義型別與使用的型別不一致
25 Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that test for the edges of multiple clocks
-------同一程序中含有兩個或多個if(edge)條件，（一個程序中之能有一個時鐘沿）
26 Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at shift_reg.vhd(19)
27 can't infer register for signal "num[0]" because signal does not hold its outside clock edge
28Error: Can't elaborate top-level user hierarchy
29 Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32) ----------有兩
個以上賦值語句，不能確定“cs_in”的值，
30 Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design.
---------------在原始檔中找不到對應的節點“over”。
31 Error: Can't access JTAG chain
無法找到下載鏈
32 Info: Assuming node "clk" is an undefined clock
Quartus警告分析 Warning
1.Found clock-sensitive change during active clock edge at time <time> on register "<name>"
原因：vector source file中時鐘敏感訊號（如：資料，允許端，清零，同步載入等）在時鐘的邊緣同時變化。而時鐘敏感訊號是不能在時鐘邊沿變化的。其後果為導致結果不正確。
措施：編輯vector source file
2.Verilog HDL assignment warning at <location>: truncated with size <number> to match size of target (<number>
原因:在HDL設計中對目標的位數進行了設定,如:reg[4:0] a;而預設為32位, 將位數裁定到合適的大小
措施:如果結果正確,無須加以修正,如果不想看到這個警告,可以改變設定的位數
3.All reachable assignments to data_out(10) assign '0', register removed by optimization
原因:經過綜合器優化後，輸出埠已經不起作用了
4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
原因:第9腳，空或接地或接上了電源
措施:有時候定義了輸出埠，但輸出端直接賦‘0’，便會被接地，賦‘1’接電源。
如果你的設計中這些埠就是這樣用的，那便可以不理會這些warning
5.Found pins ing as undefined clocks and/or memory enables
原因:是你作為時鐘的PIN沒有約束資訊。可以對相應的PIN做一下設定就行了。
主要是指你的某些管腳在電路當中起到了時鐘管腳的作用，比如flip-flop的clk管腳，而此管腳沒有時鐘約束，因此QuartusII把“clk”作為未定義的時鐘。
措施:如果clk不是時鐘，可以加“not clock”的約束；如果是，可以在clock setting當中加入；在某些對時鐘要求不很高的情況下，可以忽略此警告或在這裡修改:Assignments>Timing analysis settings...>Individual clocks...>...
6.Timing characteristics of device EPM570T144C5 are preliminary
原因:因為MAXII 是比較新的元件在 QuartusII 中的時序並不是正式版的,要等 Service Pack
措施:隻影響 Quartus 的 Waveform
7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
措施:將setting中的timing Requirements&Option-->More Timing Setting-->setting-->Enable Clock Latency中的on改成OFF
8.Found clock high time violation at 14.8 ns on register "|counter|lpm_counter:count1_rtl_0|dffs[11]"
原因:違反了steup/hold時間，應該是後模擬，看看波形設定是否和時鐘沿符合steup/hold時間
措施:在中間加個暫存器可能可以解決問題
9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay
原因:時鐘抖動大於資料延時,當時鍾很快，而if等類的層次過多就會出現這種問題,但這個問題多是在器件的最高頻率中才會出現
措施：setting-->timing Requirements&Options-->Default required fmax 改小一些，如改到50MHZ
10.Design contains <number> input pin(s) that do not drive logic
原因:輸入引腳沒有驅動邏輯(驅動其他引腳）,所有的輸入引腳需要有輸入邏輯
措施:如果這種情況是故意的,無須理會,如果非故意,輸入邏輯驅動
11.Warning：Found clock high time violation at 8.9ns on node 'TEST3.CLK'
原因：FF中輸入的PLS的保持時間過短
措施：在FF中設定較高的時鐘頻率
12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
原因:如果你用的 CPLD 只有一組全域性時鐘時，用全域性時鐘分頻產生的另一個時鐘在佈線中當作訊號處理，不能保證低的時鐘歪斜(SKEW)。會造成在這個時鐘上工作的時序電路不可靠，甚至每次佈線產生的問題都不一樣。
措施:如果用有兩組以上全域性時鐘的 FPGA 晶片，可以把第二個全域性時鐘作為另一個時鐘用，可以解決這個問題。
13.Critical Warning: Timing requirements were not met. See Report window for details.
原因：時序要求未滿足
措施：雙擊Compilation Report-->Time Analyzer-->紅色部分（如clock setup:'clk'等）-->左鍵單擊list path,檢視fmax的SLACK REPORT再根據提示解決,有可能是程式的演算法問題
14.Can't achieve minimum setup and hold requirement <text> along <number> path(s). See Report window for details.
原因：時序分析發現一定數量的路徑違背了最小的建立和保持時間，與時鐘歪斜有關,一般是由於多時鐘引起的
措施：利用Compilation Report-->Time Analyzer-->紅色部分（如clockhold:'clk'等），在slack中觀察是hold time為負值還是setup time 為負值，然後在：Assignment-->Assignment Editor-->To中增加時鐘名(from node finder)，Assignment Name中增加和多時鐘有關的Multicycle 和Multicycle Hold選項，如hold time為負，可使Multicycle hold的值>multicycle,如設為2和1。
15: Can't analyze file -- file E://quartusii/*/*.v is missing
原因：試圖編譯一個不存在的檔案，該檔案可能被改名或者刪除了
措施：不管他，沒什麼影響
16.Warning: Can't find signal in vector source file for input pin |whole|clk10m
原因：因為你的波形模擬檔案（ vector source file ）中並沒有把所有的輸入訊號(input pin)加進去，對於每一個輸入都需要有激勵源的
17.Error: Can't name logic scfifo0 of instance "inst" -- has same name as current design file
原因：模組的名字和project的名字重名了
措施：把兩個名字之一改一下，一般改模組的名字
18.Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0
原因：模組不是在本專案生成的，而是直接copy了別的專案的原理圖和源程式而生成的，而不是用QUARTUS將檔案新增進本專案
措施：無須理會，不影響使用
19.Timing characteristics of device <name> are preliminary
原因：目前版本的QuartusII只對該器件提供初步的時序特徵分析
措施：如果堅持用目前的器件，無須理會該警告。關於進一步的時序特徵分析會在後續版本的Quartus得到完善。
20.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
原因：用analyze_latches_as_synchronous_elements setting可以讓Quaruts II來分析同步鎖存，但目前的器件不支援這個特性
措施：無須理會。時序分析可能將鎖存器分析成迴路。但並不一定分析正確。其後果可能會導致顯示提醒使用者：改變設計來消除鎖 存器
21.Warning:Found xx output pins without output pin load capacitanceassignment（網友：gucheng82提供）
原因：沒有給輸出管教指定負載電容
措施：該功能用於估算TCO和功耗，可以不理會，也可以在Assignment Editor中為相應的輸出管腳指定負載電容，以消除警告
22.Warning: Found 6 node(s) in clock paths which may be acting asripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting inclock skew
原因：使用了行波時鐘或門控時鐘，把觸發器的輸出當時鍾用就會報行波時鐘，將組合邏輯的輸出當時鍾用就會報門控時鐘
措施：不要把觸發器的輸出當時鍾，不要將組合邏輯的輸出當時鍾，如果本身如此設計，則無須理會該警告
23.Warning (10268): Verilog HDL information at lcd7106.v(63):Always Construct contains both blocking and non-blocking assignments
原因： 一個always模組中同時有阻塞和非阻塞的賦值