MT6166 RF Design Notice

Topic 
▪ MT6166 RF QVL Plan
▪ MT6166 VS MT6168 & MT6167
▪ MT6166 function block
▪ MT6166 reference circuit (TDD & Common part)
▪ Connections between MT6166 and MT6572(BB)/MT6323 (PMIC)
▪ MT6166/MT6572/MT6323 RF layout guide (TDD & Common part)
▪ RF Driver Modification (2G/TDD)
▪ MT6166 reference circuit (FDD part)
▪ MT6166/MT6572/MT6323 RF layout guide (FDD part)
▪ RF Driver Modification (FDD)
▪ TD & WCMDA co-PCB
▪ Wireless de-sense design guide

內容介紹：

MT6166 規劃使用的RF元件 (QVL)

MT6166建議使用的RF元件

MT 6166收發器射頻概述

全多模射頻解決方案(gge/wcdma/tdscdma)通過3 gpp第8版
– SAW-less Quad-band support in GGE mode (GSM850/900/1800/1900)
– 3G-FDD bands support: Band 1,2,5,8.
– 3G-TDSCDMA bands support: Band 34,39,40

26 MHz內部DCXO或外部VCTCXO操作(帶有整合AFC DAC)
– Three low noise additional Clock Drivers for clocking connectivity / peripheral IC’s
– Ultra Low power 32KHz mode

支援關鍵的RX和TX規範的RF校準功能(Image rejection, LO feedthrough, DC offset)

RF Design Note –MT6166 Pin assignment

RF Design Note – MT6166 Ball Map

2G LB LNA input 為LB_RXP and LB_RXN, 2G HB and TD B34/B39 LNA input為HB_RXP and HB_RXN

Reference Circuit Schematic: MT6166 & 周邊元件 power

Bypass Cap should be put close to MT6166.
-- VRF18-1( 4 pins in MT6166) cap loading: 470nF X4 
-- VTCXO28-1 (2 pins in MT6166; 1 pin in BB DAC) cap loading: 470nFX 2 (MT6166)+ 100nF (BB) 
-- VIO18 (1 pins in MT6166 ; many pins in BB & others ) cap loading: 1uF
-- Note: Only design value  finalized Cap value will be updated later