Intel Architectures Software Developer's Manual Volume 3A System Programming Guide Chapter 7 Section 2
7.2.2 Memory Ordering in P6 and More Recent Processor Families
The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium 4, and P6 family proces-
sors also use a processor-ordered memory-ordering model that can be further
defined as "write ordered with store-buffer forwarding." This model can be character-
ized as follows.
In a single-processor system for memory regions defined as write-back cacheable,
the following ordering principles apply (Note the memory-ordering principles for
single-processor and multiple-processor systems are written from the perspective of
software executing on the processor, where the term "processor" refers to a logical
processor. For example, a physical processor supporting multiple cores and/or
HyperThreading Technology is treated as a multi-processor systems.):
1 Reads are not reordered with other reads.
2 Writes are not reordered with older reads.
3 Writes to memory are not reordered with other writes, with the exception of
writes executed with the CLFLUSH instruction and streaming stores (writes)
executed with the non-temporal move instructions (MOVNTI, MOVNTQ,
MOVNTDQ, MOVNTPS, and MOVNTPD).
4 Reads may be reordered with older writes to different locations but not with older
writes to the same location.
5 Reads or writes cannot be reordered with I/O instructions, locked instructions, or
serializing instructions.
6 Reads cannot pass LFENCE and MFENCE instructions.
7 Writes cannot pass SFENCE and MFENCE instructions.
In a multiple-processor system, the following ordering principles apply:
1 Individual processors use the same ordering principles as in a single-processor
system.
2 Writes by a single processor are observed in the same order by all processors.
3 Writes from an individual processor are NOT ordered with respect to the writes
from other processors.
4 Memory ordering obeys causality (memory ordering respects transitive
visibility).
5 Writes to the same location have a total order.
6 Locked instructions have a total order.

其實只有寫操作和其後的讀操作(不同的地址)才會亂序執行  

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