verilog中的parameter和localparam的區別
阿新 • • 發佈:2019-01-04
parameter : 全域性引數定義,可在整個設計中傳遞引數
localparam :僅限於當前模組的引數定義,跨模組不可用。
頂層例化:
mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6))
u1 (
.clka (adc_clk),
.wea (adc_wr),
.addra (adc_waddr),
.dina (adc_wdata),
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
或本模組例化
`timescale 1ns/100ps module mem #(parameter DATA_WIDTH = 16 parameter ADDR_WIDTH = 5) ( input clka, input wea, input [AW:0] addra, input [DW:0] dina, input clkb, input [AW:0] addrb, output [DW:0] doutb ); localparam DW = DATA_WIDTH - 1; localparam AW = ADDR_WIDTH - 1; reg [DW:0] m_ram[0:((2**ADDR_WIDTH)-1)]; reg [DW:0] doutb; always @(posedge clka) begin if (wea == 1'b1) begin m_ram[addra] <= dina; end end always @(posedge clkb) begin doutb <= m_ram[addrb]; end endmodule
原文地址:https://blog.csdn.net/yang2011079080010/article/details/51507904