#include

#include

/*

 *************************************************************************

 *

 * Jump vector table as in table 3.1 in [1]

 *

 *************************************************************************

 */

.globl _start

_start:        b       start_code

         ldr     pc, _undefined_instruction

         ldr     pc, _software_interrupt

         ldr     pc, _prefetch_abort

         ldr     pc, _data_abort

         ldr     pc, _not_used

         ldr     pc, _irq

         ldr     pc, _fiq

_undefined_instruction:      .word undefined_instruction

_software_interrupt:    .word software_interrupt

_prefetch_abort:          .word prefetch_abort

_data_abort:                .word data_abort

_not_used:                  .word not_used

_irq:                    .word irq

_fiq:                     .word fiq

         .balignl 16,0xdeadbeef

/*

 *************************************************************************

 *

 * Startup Code (called from the ARM reset exception vector)

 *

 * do important init only if we don't start from memory!

 * relocate armboot to ram

 * setup stack

 * jump to second stage

 *

 *************************************************************************

 */

_TEXT_BASE:

         .word         TEXT_BASE

.globl _armboot_start

_armboot_start:

         .word _start

/*

 * These are defined in the board-specific linker script.

 */

.globl _bss_start

_bss_start:

         .word __bss_start

.globl _bss_end

_bss_end:

         .word _end

#ifdef CONFIG_USE_IRQ

/* IRQ stack memory (calculated at run-time) */

.globl IRQ_STACK_START

IRQ_STACK_START:

         .word         0x0badc0de

/* IRQ stack memory (calculated at run-time) */

.globl FIQ_STACK_START

FIQ_STACK_START:

         .word 0x0badc0de

#endif

/*

 * the actual start code

 */

start_code:

         /*

          * set the cpu to SVC32 mode

          */

         mrs   r0, cpsr

         bic    r0, r0, #0x1f

         orr    r0, r0, #0xd3

         msr   cpsr, r0

         bl      coloured_LED_init

         bl      red_LED_on

#if     defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)

         /*

          * relocate exception table

          */

         ldr     r0, =_start

         ldr     r1, =0x0

         mov  r2, #16

copyex:

         subs r2, r2, #1

         ldr     r3, [r0], #4

         str     r3, [r1], #4

         bne   copyex

#endif

#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)

         /* turn off the watchdog */

# if defined(CONFIG_S3C2400)

#  define pWTCON    0x15300000

#  define INTMSK       0x14400008        /* Interupt-Controller base addresses */

#  define CLKDIVN     0x14800014        /* clock divisor register */

#else

#  define pWTCON    0x53000000

#  define INTMSK       0x4A000008        /* Interupt-Controller base addresses */

#  define INTSUBMSK         0x4A00001C

#  define CLKDIVN     0x4C000014       /* clock divisor register */

# endif

         ldr     r0, =pWTCON

         mov  r1, #0x0

         str     r1, [r0]

         /*

          * mask all IRQs by setting all bits in the INTMR - default

          */

         mov  r1, #0xffffffff

         ldr     r0, =INTMSK

         str     r1, [r0]

# if defined(CONFIG_S3C2410)

         ldr     r1, =0x3ff

         ldr     r0, =INTSUBMSK

         str     r1, [r0]

# endif

         /* FCLK:HCLK:PCLK = 1:2:4 */

         /* default FCLK is 120 MHz ! */

         ldr     r0, =CLKDIVN

         mov  r1, #3

         str     r1, [r0]

#endif        /* CONFIG_S3C2400 || CONFIG_S3C2410 */

         /*

          * we do sys-critical inits only at reboot,

          * not when booting from ram!

          */

#ifndef CONFIG_SKIP_LOWLEVEL_INIT

         bl      cpu_init_crit

#endif

#ifndef CONFIG_SKIP_RELOCATE_UBOOT

relocate:                                /* relocate U-Boot to RAM       */

         adr    r0, _start             /* r0 <- current position of code   */

         ldr     r1, _TEXT_BASE                   /* test if we run from flash or RAM */

         cmp  r0, r1                   /* don't reloc during debug         */

         beq   stack_setup

         ldr     r2, _armboot_start

         ldr     r3, _bss_start

         sub   r2, r3, r2              /* r2 <- size of armboot            */

         add   r2, r0, r2              /* r2 <- source end address         */

copy_loop:

         ldmia         r0!, {r3-r10}                  /* copy from source address [r0]    */

         stmia          r1!, {r3-r10}                  /* copy to   target address [r1]    */

         cmp  r0, r2                   /* until source end addreee [r2]    */

         ble    copy_loop

#endif        /* CONFIG_SKIP_RELOCATE_UBOOT */

         /* Set up the stack                                                          */

stack_setup:

         ldr     r0, _TEXT_BASE         /* upper 128 KiB: relocated uboot   */

         sub   r0, r0, #CONFIG_SYS_MALLOC_LEN   /* malloc area              */

         sub   r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                 */

#ifdef CONFIG_USE_IRQ

         sub   r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)

#endif

         sub   sp, r0, #12          /* leave 3 words for abort-stack    */

clear_bss:

         ldr     r0, _bss_start               /* find start of bss segment        */

         ldr     r1, _bss_end               /* stop here                        */

         mov  r2, #0x00000000          /* clear                            */

clbss_l:str r2, [r0]                 /* clear loop...                    */

         add   r0, r0, #4

         cmp  r0, r1

         ble    clbss_l

         ldr     pc, _start_armboot

_start_armboot:  .word start_armboot

/*

 *************************************************************************

 *

 * CPU_init_critical registers

 *

 * setup important registers

 * setup memory timing

 *

 *************************************************************************

 */

#ifndef CONFIG_SKIP_LOWLEVEL_INIT

cpu_init_crit:

         /*

          * flush v4 I/D caches

          */

         mov  r0, #0

         mcr   p15, 0, r0, c7, c7, 0      /* flush v3/v4 cache */

         mcr   p15, 0, r0, c8, c7, 0      /* flush v4 TLB */

         /*

          * disable MMU stuff and caches

          */

         mrc   p15, 0, r0, c1, c0, 0

         bic    r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)

         bic    r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)

         orr    r0, r0, #0x00000002     @ set bit 2 (A) Align

         orr    r0, r0, #0x00001000     @ set bit 12 (I) I-Cache

         mcr   p15, 0, r0, c1, c0, 0

         /*

          * before relocating, we have to setup RAM timing

          * because memory timing is board-dependend, you will

          * find a lowlevel_init.S in your board directory.

          */

         mov  ip, lr

         bl      lowlevel_init

         mov  lr, ip

         mov  pc, lr

#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

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