/*
 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
 *
 * Copyright (c) 2004Texas Instruments <[email protected]>
 *
 * Copyright (c) 2001Marius Gr枚ger <[email protected]>
 * Copyright (c) 2002Alex Z眉pke <[email protected]>
 * Copyright (c) 2002Gary Jennejohn <[email protected]>
 * Copyright (c) 2003Richard Woodruff <[email protected]>
 * Copyright (c) 2003Kshitij <[email protected]>
 * Copyright (c) 2006-2008 Syed Mohammed Khasim <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <asm-offsets.h>
#include <config.h>
#include <version.h>


#define  ARMV7_USR_MODE           0x10
#define  ARMV7_FIQ_MODE           0x11
#define  ARMV7_IRQ_MODE           0x12
#define  ARMV7_SVC_MODE           0x13
#define  ARMV7_MON_MODE         0x16
#define  ARMV7_ABT_MODE           0x17
#define  ARMV7_UND_MODE           0x1b
#define  ARMV7_SYSTEM_MODE        0x1f
#define  ARMV7_MODE_MASK          0x1f
#define  ARMV7_FIQ_MASK           0x40
#define  ARMV7_IRQ_MASK           0x80


.globl _start
_start: breset
ldrpc, _undefined_instruction
ldrpc, _software_interrupt
ldrpc, _prefetch_abort
ldrpc, _data_abort
ldrpc, _not_used
ldrpc, _irq
ldrpc, _fiq
#ifdef CONFIG_SPL_BUILD
_undefined_instruction: .word _undefined_instruction
_software_interrupt:.word _software_interrupt
_prefetch_abort:.word _prefetch_abort
_data_abort:.word _data_abort
_not_used:.word _not_used
_irq:.word _irq
_fiq:.word _fiq
_pad:.word 0x12345678 /* now 16*4=64 */
#else
_undefined_instruction: .word undefined_instruction
_software_interrupt:.word software_interrupt
_prefetch_abort:.word prefetch_abort
_data_abort:.word data_abort
_not_used:.word not_used
_irq:.word irq
_fiq:.word fiq
_pad:.word 0x12345678 /* now 16*4=64 */
#endif/* CONFIG_SPL_BUILD */


.global _end_vect
_end_vect:


.balignl 16,0xdeadbeef
/*************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************/


.globl _TEXT_BASE
_TEXT_BASE:
.wordCONFIG_SYS_TEXT_BASE


#ifdef CONFIG_TEGRA2
/*
 * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
 * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
 * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
 * to pick up its reset vector, which points here.
 */
.globl _armboot_start
_armboot_start:
.word _start
#endif


/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start


.global_image_copy_end_ofs
_image_copy_end_ofs:
.word __image_copy_end - _start


.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end__ - _start


.globl _end_ofs
_end_ofs:
.word _end - _start


.globl  __int_vector_start__
__int_vector_start__:
.word  __int_vector_start - _start


.globl  __int_vector_end__
__int_vector_end__:
.word  __int_vector_end - _start


.globl  _standby_start__
_standby_start__:
.word  _standby_start - _start


.globl  _standby_end__
_standby_end__:
.word  _standby_end - _start


.globl  _standby_start_lma__
_standby_start_lma__:
.word  _standby_start_lma - _start


#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word0x0badc0de


/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif


/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word0x0badc0de


/*
 * the actual reset code
 */


reset:
blsave_boot_params
/*
* set the cpu to SVC32 mode
*/
@mov r0, #0
@cmp r0, #0
@beq reset
here:
mrsr0, cpsr
bicr0, r0, #0x1f
orrr0, r0, #0xd3   @switch to svc mode and disable irq/fiq
msrcpsr,r0


#if defined(CONFIG_ARM_A7)
@set SMP bit
mrc p15, 0, r0, c1, c0, 1
orrr0, r0, #(1<<6)
mcrp15, 0, r0, c1, c0, 1
#endif
#if defined(CONFIG_ARCH_SUN9IW1P1)
ldr     r0, =0x008000e0
ldr     r1, =0x16aa0001
str     r1, [r0]
#endif


#if defined(CONFIG_OMAP34XX)
/* Copy vectors to mask ROM indirect addr */
adrr0,

[email protected] r0 <- current position of code
addr0, r0, #[email protected] skip reset vector
movr2, #[email protected] r2 <- size to copy
addr2, r0, [email protected] r2 <- source end address
movr1, #[email protected] build vect addr
movr3, #SRAM_OFFSET1
addr1, r1, r3
movr3, #SRAM_OFFSET2
addr1, r1, r3
next:
ldmiar0!, {r3 - r10}@ copy from source address [r0]
stmiar1!, {r3 - r10}@ copy to   target address [r1]
cmpr0,

[email protected] until source end address [r2]
[email protected] loop until equal */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/* No need to copy/exec the clock code - DPLL adjust already done
* in NAND/oneNAND Boot.
*/
[email protected] put dpll adjust code behind vectors
#endif /* NAND Boot */
#endif /* CONFIG_OMAP34XX */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
blcpu_init_crit
#endif


/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldrsp, =(CONFIG_SYS_INIT_SP_ADDR)
bicsp, sp, #7 /* 8-byte alignment for ABI compliance */
ldrr0,=0x00000000


@bl  boot_standby_relocat


bl asm_UART2_open
1:     


     mov r1, #0x35
     bl uart2_out_char


     ldr r0, =test_string
      bl printascii
//bl uart0_out_char
//b 1b
blboard_init_f


/*------------------------------------------------------------------------------*/


/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 */
.globl relocate_code
relocate_code:
movr4, r0/* save addr_sp */
movr5, r1/* save addr of gd */
movr6, r2/* save addr of destination */


/* Set up the stack   */
stack_setup:
movsp, r4
    /* Set up irq stack */
add r4, r4, #12
add r4, r4, #0x2000
mrs r0, cpsr
    bic r0, r0, #0x1f
    orr r0, r0, #0x12
    msr cpsr_c, r0
mov sp, r4


    /* Set up svc stack */
sub r4, r4, #0x2000
sub r4, r4, #12
mrs r0, cpsr
    bic r0, r0, #0x1f
    orr r0, r0, #0x13
    msr cpsr_c, r0


adrr0, _start
cmpr0, r6
moveqr9, #0/* no relocation. relocation offset(r9) = 0 */
beqclear_bss/* skip relocation */


@ mov r9, #0
@ b   clear_bss


movr1, r6/* r1 <- scratch for copy_loop */
ldrr3, _image_copy_end_ofs
addr2, r0, r3/* r2 <- source end address   */


copy_loop:
ldmiar0!, {r9-r10}/* copy from source address [r0]    */
stmiar1!, {r9-r10}/* copy to   target address [r1]    */
cmpr0, r2/* until source end address [r2]    */
blocopy_loop


#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
@ldrr0, _TEXT_BASE/* r0 <- Text base */
adr r0, _start
subr9, r6, r0/* r9 <- relocation offset */
ldrr10, _dynsym_start_ofs/* r10 <- sym table ofs */
addr10, r10, r0/* r10 <- sym table in FLASH */
ldrr2, _rel_dyn_start_ofs/* r2 <- rel dyn start ofs */
addr2, r2, r0/* r2 <- rel dyn start in FLASH */
ldrr3, _rel_dyn_end_ofs/* r3 <- rel dyn end ofs */
addr3, r3, r0/* r3 <- rel dyn end in FLASH */
fixloop:
ldrr0, [r2]/* r0 <- location to fix up, IN FLASH! */
addr0, r0, r9/* r0 <- location to fix up in RAM */
ldrr1, [r2, #4]
andr7, r1, #0xff
cmpr7, #23/* relative fixup? */
beqfixrel
cmpr7, #2/* absolute fixup? */
beqfixabs
/* ignore unknown type of fixup */
bfixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
movr1, r1, LSR #4/* r1 <- symbol index in .dynsym */
addr1, r10, r1/* r1 <- address of symbol in table */
ldrr1, [r1, #4]/* r1 <- symbol value */
addr1, r1, r9/* r1 <- relocated sym addr */
bfixnext
fixrel:
/* relative fix: increase location by offset */
ldrr1, [r0]
addr1, r1, r9
fixnext:
strr1, [r0]
addr2, r2, #8/* each rel.dyn entry is 8 bytes */
cmpr2, r3
blofixloop
bclear_bss
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start


#endif/* #ifndef CONFIG_SPL_BUILD */


clear_bss:
#ifdef CONFIG_SPL_BUILD
/* No relocation for SPL */
ldrr0, =__bss_start
ldrr1, =__bss_end__
#else
ldrr0, _bss_start_ofs
ldrr1, _bss_end_ofs
movr4, r6/* reloc addr */
addr0, r0, r4
addr1, r1, r4
#endif
movr2, #0x00000000/* clear   */


clbss_l:strr2, [r0]/* clear loop...   */
addr0, r0, #4
cmpr0, r1
bneclbss_l


#ifdef CONFIG_USE_IRQ
ldr r0, __int_vector_start__
ldr r1, __int_vector_end__
sub r1, r1, r0
mov r2, #0
mov r4, r6
add r0, r0, r4
copy_int_loop:
ldmia   r0!, {r7-r8}
stmia   r2!, {r7-r8}
cmp     r2, r1


@ldr     r7, [r0]
@add     r0, r0, #4
@str     r7, [r2]
@add     r2, r2, #4
@cmp     r2, r1


blo     copy_int_loop
#endif


boot_standby_relocate:
ldr r0, _standby_start__
ldr r1, _standby_end__
ldr r2, _standby_start_lma__
adr r3, _start


add r0, r0, r3
add r1, r1, r3
add r2, r2, r3


copy_standby_loop:
ldmia   r2!, {r7-r8}
stmia   r0!, {r7-r8}
cmp     r0, r1
blo     copy_standby_loop
/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */
jump_2_ram:
/*
 * If I-cache is enabled invalidate it
 */
#ifndef CONFIG_SYS_ICACHE_OFF
mcrp15, 0, r0, c7, c5, [email protected] invalidate icache
mcr     p15, 0, r0, c7, c10, [email protected] DSB
mcr     p15, 0, r0, c7, c5, [email protected] ISB
#endif
ldrr0, _board_init_r_ofs
adrr1, _start
addlr, r0, r1
addlr, lr, r9
/* setup parameters for board_init_r */
movr0, r5/* gd_t */
movr1, r6/* dest_addr */
/* jump to it ... */
movpc, lr


_board_init_r_ofs:
.word board_init_r - _start




#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************/
cpu_init_crit:
/*
* Invalidate L1 I/D
*/
movr0, #[email protected] set up for MCR
mcrp15, 0, r0, c8, c7, [email protected] invalidate TLBs
mcrp15, 0, r0, c7, c5, [email protected] invalidate icache
mcrp15, 0, r0, c7, c5, [email protected] invalidate BP array
mcr     p15, 0, r0, c7, c10, [email protected] DSB
mcr     p15, 0, r0, c7, c5, [email protected] ISB


/*
* disable MMU stuff and caches
*/
mrcp15, 0, r0, c1, c0, 0
bicr0, r0, #[email protected] clear bits 13 (--V-)
bicr0, r0, #[email protected] clear bits 2:0 (-CAM)
@orrr0, r0, #[email protected] set bit 1 (--A-) Align   ;do not enable this bit, modified by jerry
orrr0, r0, #[email protected] set bit 11 (Z---) BTB
#ifdef CONFIG_SYS_ICACHE_OFF
bicr0, r0, #[email protected] clear bit 12 (I) I-cache
#else
orrr0, r0, #[email protected] set bit 12 (I) I-cache
#endif
mcrp15, 0, r0, c1, c0, 0


/*
* Jump to board specific initialization...
* The Mask ROM will have already initialized
* basic memory. Go here to bump up clock rate and handle
* wake up conditions.
*/
movip, [email protected] persevere link reg across call
[email protected] go setup pll,mux,memory
movlr, [email protected] restore link
movpc, [email protected] back to my caller
#endif










#define SUNXI_UART0_BASE0X01C28000
#define SUNXI_UART1_BASE0X01C28400
#define SUNXI_UART2_BASE0X01C28800
#define SUNXI_UART3_BASE0X01C28C00
#define SUNXI_UART4_BASE0X01C29000
#define SUNXI_UART5_BASE0X01C29400




//    R0a1 工作暫存器
//    R1a2
//    R2a3
//    R3a4        
//    R4v1 必須保護
//    R5v2  
//    R6v3 
//    R7v4 
//    R8v5   
//    R9v6
//    R10 sl棧限制
//    R11 fp楨指標
//    R12 ip內部過程呼叫暫存器
//    R13 sp棧指標
//    R14 lr連線暫存器
//    R15 pc程式計數器



uart0_out_char:
    push{r0, r1, r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, lr}
    mov r1, #0x39
    ldr r0, =SUNXI_UART0_BASE
    ldrbr3, [r0, #20]
    tstr3, #32
    bequart0_out_char
    strbr1, [r0]
    pop{r0, r1, r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, pc}




uart2_out_char:
    push{r0, r1, r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, lr}
    mov r1, r1
    ldr r0, =SUNXI_UART2_BASE
    ldrbr3, [r0, #20]
    tst r3, #32
    beq uart2_out_char
    strbr1, [r0]
    pop {r0, r1, r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, pc}
                         
    




//列印一個字串
printascii:
    push{r0, r1, r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, lr}
    //儲存現場
    b    2f
    //向後跳到第一個標號為2的地方
1:                 
    bl uart2_out_char
    //串列埠2輸出一個字元
    teq   r1,   #'\n'
    //判斷當前已輸出字元是否為換行符
    moveq r1,   #'\r'
    //如果是換行符的話,再自動追加回車符
    beq 1b
    //如果是換行符的話,繼續列印
    //否則,處理下一個字元-->
2: 
    teq      r0, #0
    //測試字串指標是否為空
    ldrnebr1, [r0], #1
    //字串指標不為空時載入一個字元,並且字串指標後移一個字元位置
    //字串指標為空時不執行此條命令
    teqne r1, #0
    //字串指標不為空時測試載入的字元是否為串結束字元
    //字串指標為空時不執行此條命令
    bne 1b
    //不是串結束字元,繼續列印下一字元
    //是結束字元,執行下一條指令
    //字串指標為空時執行下一條指令
    pop {r0, r1, r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, pc}
    //恢復現場,並返回
                                                                    
printch:
    //列印一個字元
    push {r0, r1, r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, lr}
    mov   r1, r0
    //欲列印之字元
    mov   r0, #0
    //進入就列印一個字元,然後判斷是否繼續列印
    b     1b
                  
                   
                      
.globl    test_string
test_string:
    .ascii "test string in uboot start.S\n", "\0"
















#ifndef CONFIG_SPL_BUILD
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE72


#define S_OLD_R068
#define S_PSR64
#define S_PC60
#define S_LR56
#define S_SP52


#define S_IP48
#define S_FP44
#define S_R1040
#define S_R936
#define S_R832
#define S_R728
#define S_R624
#define S_R520
#define S_R416
#define S_R312
#define S_R28
#define S_R14
#define S_R00


#define MODE_SVC 0x13
#define I_BIT0x80


/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */


.macro bad_save_user_regs
subsp, sp, #[email protected] carve out a frame on current
@ user stack
stmiasp, {r0 - r12}@ Save user registers (now in
@ svc mode) r0-r12
ldrr2, [email protected] set base 2 words into abort
@ stack
ldmiar2, {r2 - r3}@ get values for "aborted" pc
@ and cpsr (into parm regs)
addr0, sp, #[email protected] grab pointer to old stack


addr5, sp, #S_SP
movr1, lr
stmiar5, {r0 - r3}@ save sp_SVC, lr_SVC, pc, cpsr
movr0, [email protected] save current stack into r0
@ (param register)
.endm


.macro irq_save_user_regs
subsp, sp, #S_FRAME_SIZE
stmiasp, {r0 - r12}@ Calling r0-r12
addr8, sp, #[email protected] !! R8 NEEDS to be saved !!
@ a reserved stack spot would
@ be good.
stmdbr8, {sp, lr}^@ Calling SP, LR
strlr, [r8, #0]@ Save calling PC
mrsr6, spsr
strr6, [r8, #4]@ Save CPSR
strr0, [r8, #8]@ Save OLD_R0
movr0, sp
.endm


.macro irq_restore_user_regs
ldmiasp, {r0 - lr}^@ Calling r0 - lr
movr0, r0
ldrlr, [sp, #S_PC]@ Get PC
addsp, sp, #S_FRAME_SIZE
subspc, lr, #[email protected] return & move spsr_svc into
@ cpsr
.endm


.macro get_bad_stack
ldrr13, [email protected] setup our mode stack (enter
@ in banked mode)


strlr, [r13]@ save caller lr in position 0
@ of saved stack
mrslr, [email protected] get the spsr
strlr, [r13, #4]@ save spsr in position 1 of
@ saved stack


movr13, #[email protected] prepare SVC-Mode
@ msrspsr_c, r13
msrspsr, [email protected] switch modes, make sure
@ moves will execute
movlr, [email protected] capture return pc
movspc, [email protected] jump to next instruction &
@ switch modes.
.endm


.macro get_bad_stack_swi
subr13, r13, #[email protected] space on current stack for
@ scratch reg.
strr0, [r13]@ save R0 is value.
ldrr0, [email protected] get data regions start
@ spots for abort stack
strlr, [r0]@ save caller lr in position 0
@ of saved stack
mrsr0, [email protected] get the spsr
strlr, [r0, #4]@ save spsr in position 1 of
@ saved stack
ldrr0, [r13]@ restore r0
addr13, r13, #[email protected] pop stack entry
.endm


.macro [email protected] setup IRQ stack
ldrsp, IRQ_STACK_START
.endm


.macro [email protected] setup FIQ stack
ldrsp, FIQ_STACK_START
.endm


/*
 * exception handlers
 */
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bldo_undefined_instruction


.align 5
software_interrupt:
get_bad_stack_swi
bad_save_user_regs
bldo_software_interrupt


.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bldo_prefetch_abort


.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bldo_data_abort


.align 5
not_used:
get_bad_stack
bad_save_user_regs
bldo_not_used


#ifdef CONFIG_USE_IRQ


.align 5
irq:
    sub     lr, lr, #4                                      
    //儲存返回地址
stmfd   sp!, {r0-r12, lr}
//@; save context              
//@;暫存器壓棧
mrs     r3, spsr     
//@;讀取SPSR
stmfd   sp!, {r3}
//@;壓棧


    msr     cpsr_c, #(ARMV7_FIQ_MASK | ARMV7_IRQ_MASK | ARMV7_SVC_MODE)    
    //@;切換到SVC模式
    stmfd   sp!, {r0-r12, lr}   
//@;儲存lr_usr和其它用到的暫存器


bl      do_irq


    ldmfd   sp!, {r0-r12, lr}                  
//@;恢復SYSTEM模式暫存器
    msr     cpsr_c, #(ARMV7_FIQ_MASK | ARMV7_IRQ_MASK | ARMV7_IRQ_MODE)  
    //@;切換到IRQ模式
    ldmfd   sp!, {r3}  
//@; 資料出棧
    msr     spsr_cxsf, r3
    //@; 還原spsr


ldmfd   sp!, {r0-r12, pc}^   
//@;從異常模式返回 unknown event ignore


.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effective fiq_save_user_regs */
irq_save_user_regs
bldo_fiq
irq_restore_user_regs


#else


.align 5
irq:
get_bad_stack
bad_save_user_regs
bldo_irq


.align 5
fiq:
get_bad_stack
bad_save_user_regs
bldo_fiq


#endif /* CONFIG_USE_IRQ */

#endif /* CONFIG_SPL_BUILD */

void asm_UART2_open( void )
{
  __u32   temp=0, i;
  __u32   uart_clk;
  __u32   lcr;
  volatile unsigned int   *reg;
     int port;
             
     struct spare_boot_head_t  uboot_spare_head_local; 
void  *uart_ctrl;
__u32 apb_freq;
//return;
      uboot_spare_head.boot_data.uart_port = 2;
uboot_spare_head_local.boot_data.uart_port = 2;
    uboot_spare_head_local.boot_data.uart_gpio[0].port = 2;
uboot_spare_head_local.boot_data.uart_gpio[0].port_num = 0;
uboot_spare_head_local.boot_data.uart_gpio[0].mul_sel = 2;
                      
uboot_spare_head_local.boot_data.uart_gpio[1].port = 2;
    uboot_spare_head_local.boot_data.uart_gpio[1].port_num = 1; 
uboot_spare_head_local.boot_data.uart_gpio[1].mul_sel = 2;
port = 2;


// config clock
if(port > 7)
{
return ;
}
reg = (volatile unsigned int *)0x01c2006C;
*reg &= ~(1 << (16 + port));
for( i = 0; i < 100; i++ );
*reg |=  (1 << (16 + port));
//Bus Clock Gating Register 3 
//匯流排時鐘門控暫存器
//開啟對應串列埠的時鐘源
    
(*(volatile unsigned int *)0x01c202D8) |= (1 << (16 + port));
    //Bus Software Reset Register 4
    //軟體復位對應串列埠
        
// config uart gpio
// config tx gpio


uart_ctrl = (void *)&uboot_spare_head_local.boot_data.uart_gpio[0];

boot_set_gpio((void *)uart_ctrl, 2, 1);


     apb_freq = 24*1000*1000;



    // Set Baudrate
    uart_clk = ( apb_freq + 8*UART_BAUD ) / (16*UART_BAUD);
    lcr = UART_REG_LCR(port);
    UART_REG_HALT(port) = 1;
    UART_REG_LCR(port) = lcr | 0x80;
    UART_REG_DLH(port) = uart_clk>>8;
    UART_REG_DLL(port) = uart_clk&0xff;
    UART_REG_LCR(port) = lcr & (~0x80);
UART_REG_HALT(port) = 0;
    // Set Lin Control Register
    temp = ((PARITY&0x03)<<3) | ((STOP&0x01)<<2) | (DLEN&0x03);
    UART_REG_LCR(port) = temp;


    // Disable FIFOs
    UART_REG_FCR(port) = 0x06; 
}