2-2 Verilog 7 段譯碼器（靜態顯示）
阿新 • • 發佈：2019-01-23
使用工具：Xilinx ISE 14.7
7段譯碼器主要是由七段譯碼管組成，通過控制各個譯碼管的開與關達到顯示出16進位制數的16個數。實現過程和3-8譯碼器差不多，主要是構建一個真值表作為map，然後一一對應就行了，程式碼如下：
測試檔案：module code( <span style="white-space:pre"> </span>input wire [3:0] in,<span style="white-space:pre"> </span>//輸入的數字 <span style="white-space:pre"> </span>output reg [6:0] led,<span style="white-space:pre"> </span>//7段譯碼管的對映 <span style="white-space:pre"> </span>output reg [3:0] en<span style="white-space:pre"> </span>//顯示數字的位置，比如7為3'b111那麼在前三位都顯示7 ); <span style="white-space:pre"> </span> always @ (*) case(in) 4'b0000: begin <span style="white-space:pre"> </span>led = 7'b1000000; en = 4'b1110;<span style="white-space:pre"> </span>//0 <span style="white-space:pre"> </span>end 4'b0001: begin <span style="white-space:pre"> </span>led = 7'b1111001; en = 4'b1110;<span style="white-space:pre"> </span>//1 <span style="white-space:pre"> </span>end 4'b0010: begin <span style="white-space:pre"> </span>led = 7'b0100100; en = 4'b1101;<span style="white-space:pre"> </span>//2 <span style="white-space:pre"> </span>end <span style="white-space:pre"> </span> 4'b0011: begin <span style="white-space:pre"> </span>led = 7'b0110000; en = 4'b1100;<span style="white-space:pre"> </span>//3 <span style="white-space:pre"> </span>end 4'b0100: begin <span style="white-space:pre"> </span>led = 7'b0011001; en = 4'b1011;<span style="white-space:pre"> </span>//4 <span style="white-space:pre"> </span>end 4'b0101: begin <span style="white-space:pre"> </span>led = 7'b0010010; en = 4'b1010;<span style="white-space:pre"> </span>//5 <span style="white-space:pre"> </span>end 4'b0110: begin <span style="white-space:pre"> </span>led = 7'b0000010; en = 4'b1001;<span style="white-space:pre"> </span>//6 <span style="white-space:pre"> </span>end 4'b0111: begin <span style="white-space:pre"> </span>led = 7'b1111000; en = 4'b1000;<span style="white-space:pre"> </span>//7 <span style="white-space:pre"> </span>end <span style="white-space:pre"> </span> 4'b1000: begin <span style="white-space:pre"> </span>led = 7'b0000000; en = 4'b0111;<span style="white-space:pre"> </span>//8 <span style="white-space:pre"> </span>end 4'b1001: begin <span style="white-space:pre"> </span>led = 7'b0010000; en = 4'b0110;<span style="white-space:pre"> </span>//9 <span style="white-space:pre"> </span>end 4'b1010: begin <span style="white-space:pre"> </span>led = 7'b0001000; en = 4'b0101;<span style="white-space:pre"> </span>//A <span style="white-space:pre"> </span>end 4'b1011: begin <span style="white-space:pre"> </span>led = 7'b0000011; en = 4'b0100;<span style="white-space:pre"> </span>//b <span style="white-space:pre"> </span>end 4'b1100: begin <span style="white-space:pre"> </span>led = 7'b1000110; en = 4'b0011;<span style="white-space:pre"> </span>//C <span style="white-space:pre"> </span>end 4'b1101: begin <span style="white-space:pre"> </span>led = 7'b0100001; en = 4'b0010;<span style="white-space:pre"> </span>//d <span style="white-space:pre"> </span>end 4'b1110: begin <span style="white-space:pre"> </span>led = 7'b0000110; en = 4'b0001;<span style="white-space:pre"> </span>//E <span style="white-space:pre"> </span>end 4'b1111: begin <span style="white-space:pre"> </span>led = 7'b0001110; en = 4'b0000;<span style="white-space:pre"> </span>//F <span style="white-space:pre"> </span>end endcase endmodule
模擬結果：`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 16:20:01 11/06/2014 // Design Name: code // Module Name: C:/Documents and Settings/LAB2/test.v // Project Name: LAB2 // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: code // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module test; // Inputs reg [3:0] in; // Outputs wire [6:0] led; wire [3:0] en; // Instantiate the Unit Under Test (UUT) code uut ( .in(in), .led(led), .en(en) ); initial begin // Initialize Inputs in = 0; // Wait 100 ns for global reset to finish #50; in = 2; #50; in = 3; #50; in = 4; #50; in = 5; #50; in = 6; #50; in = 7; #50; in = 8; #50; in = 9; #50; in = 10; #50; in = 11; #50; in = 12; #50; in = 13; #50; in = 14; #50; in = 15; #50; // Add stimulus here end endmodule
很難看懂是吧，在這裡附上開發板的實際效果圖與引腳檔案的編寫（我用的是NEXYS 3 ——Spartan6 XC6LX16-CS324開發板）
效果圖如下（以7的顯示為例）：NET "in[3]" LOC = "T5"; NET "in[2]" LOC = "V8"; NET "in[1]" LOC = "U8"; NET "in[0]" LOC = "N8"; NET "en[3]" LOC = "P17"; NET "en[2]" LOC = "P18"; NET "en[1]" LOC = "N15"; NET "en[0]" LOC = "N16"; NET "led[6]" LOC = "L14"; NET "led[5]" LOC = "N14"; NET "led[4]" LOC = "M14"; NET "led[3]" LOC = "U18"; NET "led[2]" LOC = "U17"; NET "led[1]" LOC = "T18"; NET "led[0]" LOC = "T17";
注意：在控制7段譯碼管時0表示亮，1表示滅
