dsp28335的AD取樣(單次模式、連續模式、DMA傳輸)
阿新 • • 發佈：2019-01-23
//單通道單次轉換0~7對應A0~A7，8~15對應B0~B7
Uint16 Ad_Get(u8 n)
{
switch (n)
{
case 0: AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;break;
case 1: AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1;break;
case 2: AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2;break;
case 3: AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3;break;
case 4: AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4;break;
case 5: AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5;break;
case 6: AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6;break;
case 7: AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7;break;
case 8: AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8;break;
case 9: AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9;break;
case 10: AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0x0A;break;
case 11: AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x0B;break;
case 12: AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x0C;break;
case 13: AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x0D;break;
case 14: AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x0E;break;
case 15: AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0x0F;break;
default :break;
}
//Start SEQ1
AdcRegs.ADCTRL2.bit.SOC_SEQ1=1;
while(AdcRegs.ADCST.bit.INT_SEQ1 == 0);
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
switch (n)
{
case 0: return ( (AdcRegs.ADCRESULT0)>>4);break;
case 1: return ( (AdcRegs.ADCRESULT1)>>4);break;
case 2: return ( (AdcRegs.ADCRESULT2)>>4);break;
case 3: return ( (AdcRegs.ADCRESULT3)>>4);break;
case 4: return ( (AdcRegs.ADCRESULT4)>>4);break;
case 5: return ( (AdcRegs.ADCRESULT5)>>4);break;
case 6: return ( (AdcRegs.ADCRESULT6)>>4);break;
case 7: return ( (AdcRegs.ADCRESULT7)>>4);break;
case 8: return ( (AdcRegs.ADCRESULT8)>>4);break;
case 9: return ( (AdcRegs.ADCRESULT9)>>4);break;
case 10: return ( (AdcRegs.ADCRESULT10)>>4);break;
case 11: return ( (AdcRegs.ADCRESULT11)>>4);break;
case 12: return ( (AdcRegs.ADCRESULT12)>>4);break;
case 13: return ( (AdcRegs.ADCRESULT13)>>4);break;
case 14: return ( (AdcRegs.ADCRESULT14)>>4);break;
case 15: return ( (AdcRegs.ADCRESULT15)>>4);break;
default: break;
}
return 0;
}
Uint16 Ad_Get(u8 n)
{
switch (n)
{
case 0: AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;break;
case 1: AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1;break;
case 2: AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2;break;
case 3: AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3;break;
case 4: AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4;break;
case 5: AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5;break;
case 6: AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6;break;
case 7: AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7;break;
case 8: AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8;break;
case 9: AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9;break;
case 10: AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0x0A;break;
case 11: AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x0B;break;
case 12: AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0x0C;break;
case 13: AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0x0D;break;
case 14: AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0x0E;break;
case 15: AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0x0F;break;
default :break;
}
//Start SEQ1
AdcRegs.ADCTRL2.bit.SOC_SEQ1=1;
while(AdcRegs.ADCST.bit.INT_SEQ1 == 0);
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
switch (n)
{
case 0: return ( (AdcRegs.ADCRESULT0)>>4);break;
case 1: return ( (AdcRegs.ADCRESULT1)>>4);break;
case 2: return ( (AdcRegs.ADCRESULT2)>>4);break;
case 3: return ( (AdcRegs.ADCRESULT3)>>4);break;
case 4: return ( (AdcRegs.ADCRESULT4)>>4);break;
case 5: return ( (AdcRegs.ADCRESULT5)>>4);break;
case 6: return ( (AdcRegs.ADCRESULT6)>>4);break;
case 7: return ( (AdcRegs.ADCRESULT7)>>4);break;
case 8: return ( (AdcRegs.ADCRESULT8)>>4);break;
case 9: return ( (AdcRegs.ADCRESULT9)>>4);break;
case 10: return ( (AdcRegs.ADCRESULT10)>>4);break;
case 11: return ( (AdcRegs.ADCRESULT11)>>4);break;
case 12: return ( (AdcRegs.ADCRESULT12)>>4);break;
case 13: return ( (AdcRegs.ADCRESULT13)>>4);break;
case 14: return ( (AdcRegs.ADCRESULT14)>>4);break;
case 15: return ( (AdcRegs.ADCRESULT15)>>4);break;
default: break;
}
return 0;
}