linux 中斷與異常---mips基礎（一）

阿新 • • 發佈：2019-02-04

MIPS體系結構採用的是精確異常處理模式這是什麼意思呢？下面來看從“See MIPS Run”一書中的摘錄：“In a precise-exception CPU, on anyexception we get pointed at one instruction(the exception victim). All instructions preceding theexception victim in execution sequence are complete; any work done on the victim and on anysubsequent instructions (BNN NOTE: pipeline effects) has no side effects that the software need worry about. The software that handles exceptions can ignore all the timing effects of the CPU's implementations”

上面的意思其實很簡單：在發生這個異常之前的一切計算行為會完整的結束並體現效果。在發生這個異常之後的一切計算行為（包含當前這條指令）將不會產生任何效果。另外一種解釋是：Aprecise exceptionis one in which the EPC (CP0, Register 14, Select 0) can be used to identify the instruction that caused the exception. For imprecise exceptions, the instruction that caused the exception cannot be identified. Most exceptions are precise. Bus error exceptions may be imprecise.

異常處理的一般過程

With the exception of Reset, Soft Reset, NMI, and Debug exceptions, which have their own special processing asdescribed below, exceptions have the same basic processing flow:• If the EXL bit in theStatusregister is cleared, theEPCregister is loaded with the PC at which execution will berestarted and the BD bit is set appropriately in the

Causeregister. If the instruction is not in the delay slot of a branch,the BD bit inCausewill be cleared and the value loaded into theEPCregister is the current PC. If the instruction isin the delay slot of a branch, the BD bit inCauseis set andEPCis loaded with PC-4.If the EXL bit in theStatusregister is set, theEPCregister is not loaded and the BD bit is not changed in theCauseregister.• The CE and ExcCode fields of theCauseregisters are loaded with the values appropriate to the exception. The CEfield is loaded, but not defined, for any exception type other than a coprocessor unusable exception.• The EXL bit is set in theStatusregister.• The processor is started at the exception vector.The value loaded intoEPCrepresents the restart address for the exception and need not be modified by exception handlersoftware in the normal case. Softwareneed notlook at the BD bit in theCauseregister unless is wishes to identify theaddress of the instruction that actually caused the exception.Note that individual exception types may load additional information into other registers. This is noted in the descriptionof each exception type below.EPC中存放的是異常發生時執行的指令地址，或者分支延時發生異常，則存放的是分支的指令地址，不管怎麼樣，異常處理函式返回都從EPC開始恢復執行，如果在分支延時指令發生異常，則需要在cause暫存器中存放相應標誌，這樣就可以準確的知道發生異常的指令地址了。Operation:ifStatusEXL= 0 then if InstructionInBranchDelaySlot then EPC <- PC - 4 CauseBD<- 1 else EPC <- PC CauseBD<- 0 endif if ExceptionType = TLBRefill then vectorOffset <- 0x000 elseif (ExceptionType = Interrupt) and (CauseIV= 1) then vectorOffset <- 0x200 else vectorOffset <- 0x180 endifelse vectorOffset <- 0x180endifCauseCE<- FaultingCoprocessorNumberCauseExcCode<- ExceptionTypeStatusEXL<- 1if StatusBEV= 1 then PC <- 0xBFC0_0200 + vectorOffsetelse PC <- 0x8000_0000 + vectorOffsetendifAs with any procedure, the exception handler must save any registers it may modify, and then restore thembefore returning control to the interrupted program. Saving registers in memory poses a problem in MIPS:addressing the memory requires a register (the base register) in which the address is formed. This means that a register must be modified before any register can be saved! The MIPS register usage convention (see Laboratory4) reserves registers$26and$27($k0and$k1) for the use of the interrupt handler. This meansthat the interrupt handler can use these registers without having to save them first. A user program that usesthese registers may find them unexpectedly changed.The CPU operates in one of the two possible modes,userandkernel.User programs run in user mode. TheCPU enters the kernel mode when an exception happens. Coprocessor 0 can only be used in kernel mode.說明：為何分支延時槽中的指令發生異常要從分支指令重新執行呢，這是因為mips的指令執行是流水線結構，分析指令的執行結果不會影響到延時槽中指令的執行，也就是說不管分支指令往哪裡跳，延時槽的指令都會執行，如果EPC儲存延時指令地址，則分析指令執行的結果將會丟失，這樣異常處理結束後恢復執行的結果就不正確

異常入口（向量）

TheReset,Soft Reset, andNMIexceptions are always vectored to location 0xBFC0_0000. Debug exceptions arevectored to location 0xBFC0_0480 or to location 0xFF20_0200 if the ProbTrap bit is 0 or 1, respectively, in theEJTAGControl register(ECR). Addresses forall other exceptionsare a combination of a vector offset and a base address.Table4-2 gives thebase addressas a function of the exception and whether the BEV bit is set in theStatusregister.

Table 4-3 gives theoffsetsfrom the base address as a function of the exception.

CauseIV:Setting the CP0CauseIVbit to 1 causes Interrupt exceptions to use a dedicated exception vector offset (0x200), rather than having to use the general exception vector offset (0x180).Table 4-4combines these two tables into one thatcontains all possible vector addresses as a function of the state that can affect the vector selection.

In MIPS32®Release 2 and higher architectures, software is allowed to specify the vector base address via the CP0Ebaseregister for exceptions that occur when CP0StatusBEVequals 0.

StatusBEV= 1: Exceptions vector to an uncached entry point in KSEG1: 0xBFC00xxx
StatusBEV= 0: Exceptions vector to cached entry points in KSEG0: defined by CP0 Ebase register, plus some offset

Note:StatusBEV= 1 at reset.IfEbaseis to be changed, it must be done withStatusBEV= 1(i.e. at system boot). The operation of the CPU isUNDEFINEDifEbaseis written whenStatusBEV= 0.The Ebase default is 0x8000_0000 after reset.EBase暫存器是一個可讀寫暫存器，包含例外向量基地址和一個只讀的CPU號。

對Cache Error這個特殊的異常來說，需要給他安排一個任何時候都是Uncached的基地址了。因為發生這個異常時Cache已經不可靠了，在處理它是就不能使用它了。因此這個異常的入口基地址為： BEV = 1 : BFC0,0300 （系統啟動地址空間 : kseg1） BEV = 0 : [SP]: A000,0000 （實體記憶體地址 : kseg1） [MP]: EBASE[31.30] || 1 || EBASE[28...12] || 0x000 （實體記憶體地址 : kseg1）上面的總結一下：Reset,Soft Reset和NMI：不受任何配置的影響，異常向量位置總是在0XBFC0_0000General Exception：異常向量在0xBFC0_0200 + 0x180 或 Ebase + 0x180Interrupt：IV 表示是否使用專用的異常處理向量， IV=0，採用General Exception中斷向量， IV=1，則採用int專用的中斷向量TLB refill：EXL為0時，採用TLB refill專用的異常處理向量，EXL為1時，採用General Exception中斷向量

異常優先順序

所謂的優先順序是指：當在某個時刻，同時多個異常或中斷出現時，CPU將會按照上述的優先順序來處理。

前面一列為exception的編號，後面一列為改異常的描述

異常相關暫存器

The BadVAddr registerThis register (its name stands forBad VirtualAddress) will contain the memory address where the exceptionhas occurred. An unaligned memory access, for instance, will generate an exception and the address wherethe access was attempted will be stored in BadVAddr.SR(Status Register，狀態暫存器)EXLException Level; set by the processor when any exception other than Reset, Soft Reset, NMI, or Cache Error exception are taken. 0: normal 1: exception當EXL被置位時，- 中斷是被禁止的。換句話說，這時SR[IE]位是不管用了，相當於所有的中斷都被遮蔽了。- TLB Refill異常將會使用General Exception Vector而不是預設的TLB Refill Vector.- 如果再次發生異常，EPC將不會被自動更新。這一點要非常注意。如果想支援巢狀異常，要在異常處理例程中清EXL位。當然要先儲存EPC的值。另外要注意的：MIPS當陷入Exception/Interrupt時，並不改變SR[UX],SR[KX]或SR[SX]的值。SR[EXL]為1自動的將CPU mode執行在核心模式下。這一點要注意。ERLError Level; set by the processor when Reset, Soft Reset, NMI, orCache Error exceptionare taken. 0: normal 1: error當ERL被置位時，- 中斷被禁止。- 中斷返回ERET使用的是ErrorEPC而不是EPC。需要非常注意這個區別。-Kuseg和xkuseg 被認為是沒有對映(Mapped)的和沒有快取（Un-Cached）。可以這樣理解，MIPS CPU只有在這個時刻才是一種真實模式(real mode)，可以不需要TLB的對映，就直接使用kuseg的地址空間。The ERET instruction to return from exception is used for returning fromexception level (Status.EXL) and error level (Status.ERL). If both bitsare set however we should be returning from ERL first, as ERL caninterrupt EXL, for example when an NMI is taken.都是通過eret返回的，如果EXL和ERL同時設定了，則應該首先從ERL返回，PC設定為ErrorPC,清除ERL，注意這時不會清除EXLERET指令用模擬器實現的程式碼大致如下：if (kvm_read_c0_guest_status(cop0) & ST0_ERL) { kvm_clear_c0_guest_status(cop0, ST0_ERL); vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0); } else if (kvm_read_c0_guest_status(cop0) & ST0_EXL) { kvm_clear_c0_guest_status(cop0, ST0_EXL); vcpu->arch.pc = kvm_read_c0_guest_epc(cop0);}IEInterrupt Enable 0: disable interrupts 1: enable interrupts。請記住：當SR[EXL]或SR[ERL]被SET時， SR[IE]是無效的。BEV Normal/Bootstrap exception vectors locationSRSoft Reset,如果是soft reset，該位置1，表明是軟體復位NMI如果是NMI，該位置1，表明是不可遮蔽中斷IM[7:0]Interrupt MaskUMKernel/User Mode， UM=1使用者模式，中斷髮生時不改變該bit的值UM:ERL:EXL Mode100: User000: Kernel-10: Kernel (exception handling)-01: Kernel (error handling)Cause

BD: Exception happened in a branch delay slotIV: Use general vs special

linux 中斷與異常---mips基礎（一）

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