使用FPGA實現各種演算法時，狀態機是很常用的方法，在SysGen中有兩種非常簡便的方法構建狀態機，一是使用Mcode，以switch-case語句輕鬆實現，二是使用SysGen自帶狀態機模組。

     狀態機

假設我們要從01序列中檢測出1011序列，則狀態機模型如下

Next State Matrix：[0 1; 2 1; 0 3; 2 1]

Output Matrix ： [0 0; 0 0; 0 0; 0 1]

一、使用Mcode實現

上一篇部落格講解了在Sysgen中Mcode的限制能力，這裡直接使用

構建模型如下：

Singal From Workspace用於產生一個01序列，作為輸入訊號。

gatwayIn將資料型別轉化為UFix_1_0

新增Mcode函式stateMcode.m

function [nextState, matched] = stateMcode(currentState, din)
% This is the update function for detecting a pattern of 1011
% This function represents a stateless and combination logic block.
% The output nextState should be to a register, and the output
% of the register should be fed back to the input currentState.
% Because the state register block has a feed back connection, in
% order to propagate the port prototypes automatically, the prototype
% of nextState should be determined only by constants or through
% an explicity xfix() call.

  seen_none = 0; % initial state, if input is 1, switch to seen_1
  seen_1 = 1;    % first 1 has been seen, if input is 0, switch
                 % seen_10
  seen_10 = 2;   % 10 has been detected, if input is 1, switch to
                 % seen_1011
  seen_101 = 3;  % now 101 is detected, is input is 1, 1011 is
                 % detected and the FSM switches to seen_1

  % the default value of matched is false
  matched = false;

  switch currentState
   case seen_none
    if din==1
      nextState = seen_1;
    else
      nextState = seen_10;
    end
   case seen_1 % seen first 1
    if din==1
      nextState = seen_1;
    else
      nextState = seen_10;
    end
   case seen_10 % seen 10
    if din==1
      nextState = seen_101;
    else
      % no part of sequence seen, go to seen_none
      nextState = seen_none;
    end
   case seen_101
    if din==1
      nextState = seen_1;
      matched = true;
    else
      nextState = seen_10;
      matched = false;
    end
   otherwise
    % if nextState is not assigned outside the switch statement,
    % an otherwise statment is required
    nextState = seen_none;
  end

 

Scope效果如圖：

二、使用Mealy State Machine模組實現

構建模型：

設定Mealy State Machine引數，就是狀態機的引數

模擬結果如下：

在進行FPGA影象處理時，經常會用到狀態機，這幾天剛學習過，記錄一下，其實使用Verilog直接實現也不是很難，只是會比SysGen稍微麻煩一些，修改起來也會花費更多的時間。

Model Based Design 在Xilinx 的工具中逐漸得到加強，相信以後會更加的方便。