entity testbench is end testbench; architecture Behavioral of testbench is
component fredevider3 is
port(
    clock:in std_logic;     reset:in std_logic;
    clkout:out std_logic
);
end component fredevider3;
constant clk_period:time:=100 ns; signal reset:std_logic:='0';
signal clk1: std_logic:='0';
signal clk2: std_logic;
begin
u1: fredevider3
port map(
    clock=>clk1,     reset=>reset,
    clkout=>clk2
); --產生時鐘訊號
process
begin
clk1<='1';
wait for clk_period/2;
clk1<='0';
wait for clk_period/2;
end process; --產生reset訊號 process begin wait for 100ns; reset<='1'; wait for 100ns; reset<='0'; wait; end process; end Behavioral;