【Vivado那些事】Xilinx FPGA普通IO能不能直接接入PLL作為時鐘輸入

阿新 • • 發佈：2021-01-20

[結論]

普通IO不能直接作PLL的時鐘輸入,專用時鐘管腳可以;

普通IO可以通過BUFG再連到PLL的時鐘輸入上,但要修改PLL的設定 input clk的選項中要選擇"No Buffer";

具體內部佈局分配可以通過 Xilinx的FPGA Editor來檢視,

ZYNQ的時鐘管理也和之前的片子略有不同,之後在另一篇介紹,相關文件 <ug472_7Series_Clocking.pdf>

[Demo1]

1 // demo1 two bufg connect
 2 
 3 module iobuf(
 4 
 5  input clk,
 6 
 7  input     rst,
 8 
 9  output   led
10 
11  );
12 
13  wire clkin_w;
14 
15  BUFG BUFG_inst (
16 
17       .O(clkin_w),           // Clock buffer output
18 
19       .I(clk)                   // Clock buffer input
20 
21    );
22 
23  pll0 u_pll0(
24 
25     .CLK_IN1(clkin_w),      // IN
26 
27     .CLK_OUT1(clkout),  // OUT
28 
29     .RESET(rst));       // IN
30 
31 assign led = clkout;
32 
33 endmodule

鎖相環PLL預設輸入前端有個BUFG單元,而兩個BUFG不能相連,所以會報這樣的錯:

ERROR:NgdBuild:770 - IBUFG ‘u_pll0/clkin1_buf’ and BUFG ‘BUFG_inst’ on
net

‘clkin_w’ are lined up in series. Buffers of the same direction
cannot be

placed in series.

ERROR:NgdBuild:924 - input pad net ‘clkin_w’ is driving non-buffer
primitives:

[Demo2]

1 // demo2 regular io directly connect to PLL
 2 
 3 module iobuf(
 4 
 5     input clk,
 6 
 7  input     rst,
 8 
 9  output   led
10 
11  );
15  wire clkin_w;
16 
17  /*
18 
19  BUFG BUFG_inst (
20 
21       .O(clkin_w),           // Clock buffer output
22 
23       .I(clk)                   // Clock buffer input
24 
25    );
26 
27 */
28 
29  pll0 u_pll0(
30 
31     .CLK_IN1(clk),      // IN
32 
33     .CLK_OUT1(clkout),  // OUT
34 
35     .RESET(rst));       // IN
36 
37 assign led = clkout;
38 
39 endmodule

普通IO不能直接做鎖相環的輸入,所以會報這樣的錯:

ERROR:Place:1397 - A clock IOB / MMCM clock component pair have been
found that

are not placed at an optimal clock IOB / MMCM site pair. The clock
IOB

component is placed at site . The corresponding MMCM
component

<u_pll0/mmcm_adv_inst> is placed at site <MMCME2_ADV_X0Y0>. The

clock IO can

use the fast path between the IOB and the MMCM if the IOB is placed
on a

Clock Capable IOB site that has dedicated fast path to MMCM sites
within the

same clock region. You may want to analyze why this problem exists
and

correct it. If this sub optimal condition is acceptable for this
design, you

may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to
demote this

message to a WARNING and allow your design to continue. However,
the use of

this override is highly discouraged as it may lead to very poor
timing

results. It is recommended that this error condition be corrected
in the

design. A list of all the COMP.PINs used in this clock placement
rule is

ERROR:Pack:1654 - The timing-driven placement phase encountered an
error.

如果有ucf中加上這句約束:

NET clk          CLOCK_DEDICATED_ROUTE = FALSE;

依舊會報錯,在ZYNQ7000系列,這樣還是通不過,如下:

ERROR:PhysDesignRules:2256 - Unsupported MMCME2_ADV configuration. The
signal

u_pll0/clkin1 on the CLKIN1 pin of MMCME2_ADV comp
u_pll0/mmcm_adv_inst with

COMPENSATION mode ZHOLD must be driven by a clock capable IOB.

ERROR:Pack:1642 - Errors in physical DRC.

使用普通的IO,再連線bufg來連到時鐘線上,

仍會報這樣的錯誤,因為還是兩bufg相連了:

ERROR:NgdBuild:770 - IBUFG ‘u_pll0/clkin1_buf’ and BUFG ‘BUFG_inst’ on
net

‘clkin_w’ are lined up in series. Buffers of the same direction
cannot be

placed in series.

ERROR:NgdBuild:924 - input pad net ‘clkin_w’ is driving non-buffer
primitives:

[Demo3]

// dem3 regular io with BUFG then connect to PLL which with"No Buffer" setting

 module iobuf(

 input clk,

 input     rst,

 output   led

 );

 wire clkin_w;

 BUFG BUFG_inst (

      .O(clkin_w),           // Clock buffer output

      .I(clk)                   // Clock buffer input

   );

 pll0 u_pll0(

    .CLK_IN1(clkin_w),      // IN

    .CLK_OUT1(clkout),  // OUT

    .RESET(rst));       // IN

assign led = clkout;

endmodule