奇偶分頻電路verilog程式碼

1.偶數分頻器

偶數分頻器只要在計數器為N/2-1時反轉輸出就行

//4分頻器
module clk_div(
    input clk,
    input rst_n,
    output reg clk_div4
);
    reg [3:0]count;
    parameter N=4;//若用integer i 採用
    
    always@(posedge clk or negedge rst_n)begin
    if(rst_n)
    begin
        count <=4'b0;
    end
    else if(count==4'b1)
    begin
        count <=4'b0;
    end
    else begin
        count <=count +4'd1;
    end
    end

    always @(posedge clk or negedge rst_n)begin
        if(rst_n)begin
            clk_div4 <=1'b0;
        end
        else if(count==4'b1)begin
            clk_div4<=~clk_div4;
        end
        else begin
            clk_div4<=clk_div4;
        end
    end

endmodule
 

2.奇數分頻器

奇數分頻器有兩種，一種是佔空比為50的一種是佔空比非20的。

首先是佔空比非50的，用錯位異或實現

module div5(
    input clk,
    input rst_n,
    output clk_div5
);
    reg clk1;
    reg clk2;
    reg [2:0] count;

    always @(posedge clk or negedge rst_n) begin
        if(rst_n)begin
            count <=3'd0;
        end
        else if(count==3'd4)begin
            count <=3'd0;
        end
        else begin
            count <=count+1'b1;
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if(rst_n)begin
            clk1<=1'b0;
        end
        else if(count==3'd4)begin
            clk1 <=~clk1;
        end
        else begin
            clk1<=clk1;
        end

    end

    always @(posedge clk or negedge rst_n) begin
        if(rst_n)begin
            clk2<=1'b0;
        end
        else if(count==3'd2)begin
            clk2 <=~clk2;
        end
        else begin
            clk2<=clk2;
        end

    end
    assign clk_div5 = clk2^clk1 ;
endmodule
 

關鍵是第一個clk等計數器=N-1跳，第二個在(N-1)/2跳

接下來是50佔空比的，用另一個下降沿實現

module top(
    input clk,
    input rst_n,
    output clk_div
);
    reg clk1;
    reg clk2;
    reg [2:0] count;

    always @(posedge clk or negedge rst_n) begin
        if(rst_n)begin
            clk1 <=1'd0;
        end
        else if(count==3'd0)begin
            clk1 <=1'd1;
        end
        else if(count==3'd2)begin
            clk1 <=1'b0;
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if(rst_n)begin
            count <=3'd0;
        end
        else if(count==3'd4)begin
            count <=3'd0;
        end
        else begin
            count <=count+1'b1;
        end
    end


    always @(negedge clk or negedge rst_n) begin
        if(rst_n)begin
            clk2<=1'b0;
        end
        else  begin
            clk2<=clk1;
        end

    end
    assign clk_div = clk2 || clk1 ;
endmodule
 

關鍵在第一個於（N-1）/2的時候從1跳0，第二個下降沿觸發，相當於第一個的後一級暫存器。