HDLs use z to indicate a floating value. z is particularly useful for describing a tristate buffer, whose output floats when the enable is 0. A bus can be driven by several tristate buffers, exactly one of which should be enabled. If the buffer is enabled, the output is the same as the input. If the buffer is disabled, the output is assigned a floating value (z). Similarly, HDLs use x to indicate an invalid logic level. If a bus is simultaneously driven to 0 and 1 by two enabled tristate buffers (or other gates), the result is x, indicating contention. If all of the tristate buffers driving a bus are simultaneously OFF, the bus will float, indicated by z.

At the start of simulation, state nodes such as flip-flop outputs are initialized to an unknown state (x in SystemVerilog and u in VHDL). This is helpful to track errors caused by forgetting to reset a flip-flop before its output is used.

If a gate receives a floating input, it may produce an x output when it can't determine the correct output value. Similarly, if it receives an illegal or uninitialized input, it may produce an x output.

Seeing x or u values in simulation is almost always an indication of a bug or bad coding practice. In the synthesized circuit, this corresponds to a floating gate input, uninitialized state, or contention. The x or u may be interpreted randomly by the circuit as 0 or 1, leading to unpredictable behavior.

Often it is necessary to operate on a subset of a bus or to concatenate (join together) signals to form busses. These operations are collectively known as bit swizzling [混合; 攪拌].

Delays are ignored during synthesis; the delay of a gate produced by the synthesizer depends on its tpd and tcd specifications, not on numbers in HDL code. #n表示有n個時間單位的延時，不是在第n個節拍發生。見過有演示程式寫成#1 #2 #3 ... #10。In VHDL, the after clause is used to indicate delay.

In SystemVerilog, expressions such as ~s are permitted in the port list for an instance. Arbitrarily complicated expressions are legal but discouraged because they make the code difficult to read. 如: tristate t0(d0, ~s, y); In VHDL, expressions such as not s are not permitted in the
port map for an instance. Thus, sbar must be defined as a separate signal. bar就是非a的數學符號裡a頭上那道槓。

In general, complex systems are designed hierarchically. The overall system is described structurally by instantiating its major components. Each of these components is described structurally from its building blocks and so forth recursively until the pieces are simple enough to describe behaviorally.

The vast majority of modern commercial systems are built with registers using positive edge-triggered D flip-flops.

In SystemVerilog always statements and VHDL process statements, signals keep their old value until an event in the sensitivity list takes place that explicitly causes them to change. Hence, such code, with appropriate sensitivity lists, can be used to describe sequential circuits with memory. For example, the flip-flop includes only clk in the sensitive list. It remembers its old value of q until the next rising edge of the clk, even if d changes in the interim [在其間].

In contrast, SystemVerilog continuous assignment statements (assign) and VHDL concurrent assignment statements (<=) are reevaluated whenever any of the inputs on the right-hand side change. Therefore, such code necessarily describes combinational logic.

A SystemVerilog always statement is executed only when the event specified in the sensitivity list occurs. MFC程式設計師表示ON_SIGNAL更好理解。Sensitivity lists are also referred to as stimulus lists. 人人都說人腦高，有事沒事往上靠。

always statements can be used to imply flip-flops, latches, or combinational logic, depending on the sensitivity list and statement. Because of this flexibility, it is easy to produce the wrong hardware inadvertently. SystemVerilog introduces always_ff, always_latch, and always_comb to reduce the risk of common errors. always_ff behaves like always but is used exclusively to imply flip-flops and allows tools to produce a warning if anything else is implied.

An alternative VHDL idiom for a flip-flop is

process(clk) begin
if clk'event and clk = '1' then
q <= d;
end if;
end process;

rising_edge(clk) is synonymous with clk'event and clk = '1'.

Generally, it is good practice to use resettable registers so that on powerup you can put your system in a known state.

always_ff @(posedge clk, posedge reset) // asynchronous reset
always_ff @(posedge clk) // synchronous reset

The asynchronously resettable flop immediately responds to a rising edge on reset, but the synchronously resettable flop responds to reset only on the rising edge of the clock.

Enabled registers respond to the clock only when the enable is asserted.

Not all synthesis tools support latches well. Unless you know that your tool does support latches and you have a good reason to use them, avoid them and use edge-triggered flip-flops instead. If you don’t know whether you intended to have a latch or not, you are probably approaching HDLs like a programming language and have bigger problems lurking. 好像說得就是我啊。高階語言裡op = instruction[5:0]，然後多次使用op是種手工優化，Verilog裡我後來換複製貼上instruction[5:0]了。