System Verilog (2) 字串
阿新 • • 發佈:2022-03-29
除去 logic, bit, byte, int, shortint, longint 等基本變數外,還有下列資料型別
(1) 字串 string
字串的宣告,大小,列印操作
module string_basic; string dialog = "helloworld" ; initial begin $display ("%s", dialog); $display("string name = %s", dialog); $display("string size = %0d",$size(dialog)); foreach (dialog[i]) begin $display("%s",dialog[i]); end end endmodule
編譯結果
# Loading sv_std.std
# Loading work.string_basic(fast)
#
# vsim -voptargs=+acc=npr
# run -all
# helloworld
# string name = helloworld
# string size = 10
# h
# e
# l
# l
# o
# w
# o
# r
# l
# d
# exit
# End time: 07:30:26 on Mar 29,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
Done
字串可以比較、賦值
module string_operation; string firstname = "taylor" ; string lastname = "swift" ; initial begin if (firstname == lastname) $display("firstname %s == lastname %s",firstname,lastname); else $display("firstname %s != lastname %s",firstname,lastname); if (firstname <= lastname) $display("firstname %s <= lastname %s",firstname,lastname); else if (firstname >= lastname) $display("firstname %s >= lastname %s",firstname,lastname); end initial begin $display("fullname is %s ",{firstname,lastname}); $display("repeatname = %s",{3{firstname}}); $display("firstname[2]=%s, lastname[2]=%s",firstname[2],lastname[2]); foreach(firstname[i]) begin $display("firstname[%0d]=%s",i,firstname[i]); end end endmodule
編譯結果
# Loading sv_std.std # Loading work.string_operation(fast) # # vsim -voptargs=+acc=npr # run -all # firstname taylor != lastname swift # firstname taylor >= lastname swift # fullname is taylorswift # repeatname = taylortaylortaylor # firstname[2]=y, lastname[2]=i # firstname[0]=t # firstname[1]=a # firstname[2]=y # firstname[3]=l # firstname[4]=o # firstname[5]=r # exit # End time: 07:52:22 on Mar 29,2022, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Done
通過編譯結果可以看出,字串的索引號是從左往右開始編號的,和佇列相似