System Verilog (7) 佇列
阿新 • • 發佈：2022-03-31
檢視程式碼
module tb; int q1[$]={1,2,3,4,5}; int q2[$]; int tmp; initial begin tmp = q1[0]; #1; tmp = q1[$]; #1; q2 = q1; #1; q2 = {}; #1; q2[0] = 15; #1; q2.insert(0,15); #1; q2 = {q2,22}; #1; q2 = {99,q2}; #1; q2 = q2[1:$]; #1; q2 = q2[0:$-1]; #1; q2 = q2[1:$-1]; #1; end initial begin $monitor("time %0t ns tmp=%0d q2=%p", $time, tmp,q2); end endmodule
編譯結果
# Loading sv_std.std # Loading work.tb(fast) # # vsim -voptargs=+acc=npr # run -all # time 0 ns tmp=1 q2='{} # time 1 ns tmp=5 q2='{} # time 2 ns tmp=5 q2='{1, 2, 3, 4, 5} # time 3 ns tmp=5 q2='{} # time 4 ns tmp=5 q2='{15} # time 5 ns tmp=5 q2='{15, 15} # time 6 ns tmp=5 q2='{15, 15, 22} # time 7 ns tmp=5 q2='{99, 15, 15, 22} # time 8 ns tmp=5 q2='{15, 15, 22} # time 9 ns tmp=5 q2='{15, 15} # time 10 ns tmp=5 q2='{} # exit # End time: 08:19:51 on Mar 31,2022, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 Done
將類的指標/控制代碼宣告為佇列
class fruit; string name; function new (string name = "unknown"); this.name=name; endfunction endclass module tb; fruit list[$]; initial begin fruit f=new("apple"); list.push_back(f); f=new("banana"); list.push_back(f); foreach(list[i]) begin $display("list[%0d]=%s",i,list[i].name); end $display("list = %p",list); end endmodule
編譯結果
# Loading sv_std.std
# Loading work.testbench_sv_unit(fast)
# Loading work.tb(fast)
#
# vsim -voptargs=+acc=npr
# run -all
# list[0]=apple
# list[1]=banana
# list = '{@fruit@1, @fruit@2}
# exit
# End time: 08:43:29 on Mar 31,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
Done