地址發生器

module add_produce(en,clk,d_out);
    input clk,en;
    output[7:0] d_out;
    reg[7:0] = Q; 
    reg full;
    always@(posedge clk)
        if(en)        
            begin
                if(full != 1)
                    begin Q <= Q+1;full <= 0;end 
                else
                    begin
 
 Q <= 0;full <= 0; end
            end 
        else
            begin Q <= 0;full <= 0; end
            
        assign full = (Q == 2‘h7F);
        assign d_out = Q;        
endmodule            

rom加載mif文件

module lp_rom(clk,data,d_out);
    input[7:0] data;
    input clk;
    output[7:0] d_out;
    
 
reg[7:0] Q,d_out;
    reg[7:0] mem[127:0] /*synthesis rom_init_file="ROM_78.mif" */;
    always@(data)
        Q <= mem[data];
    always@(posedge clk)
        d_out = Q;
endmodule    

整合成正弦波發生器

module sin_gnt(en,clk,data,d_out);
    input en,clk;
    input[7:0] data;
    output[7:0] d_out;
    wire[7
 
:0] address;
    add_produce ad(.en(en),.clk(clk),.d_out(address));
    lp_rom lr(.clk(clk),.data(address),.d_out(d_out));
endmodule    

rom正弦波發生器