基於移位加法的乘法器---Verilog實現
阿新 • • 發佈:2018-11-15
無符號數的乘法,根據乘數的數位計算位積,再將一系列位積相加。便可以得到兩個無符號二進位制數的乘積。這裡可以選擇移位的方式。比如out= in * 13,in為4位,則out為8位,的計算:assign out = a + a << 2 + a <<3;實現。
組合邏輯電路乘法器實現:
module mult_module#(
parameter WIDTH = 8
)
(
input [WIDTH-1:0] S_data1,
input [WIDTH-1:0] S_data2,
output reg [2*WIDTH-1:0] F_mult
);
integer index;
reg [2*WIDTH-1:0] S_data2_temp;
[email protected](*)
begin
F_mult = 0;
S_data2_temp = { {WIDTH{1'b0}}, S_data2 };
for(index = 0;index <WIDTH ; index = index + 1 )
begin
F_mult = F_mult + ({ 2*WIDTH{S_data1[index]}} & (S_data2_temp << index));
end
end
endmodule
模擬檔案:
module tb_mult_module(
);
parameter WIDTH = 8;
reg [WIDTH-1:0] S_data1;
reg [WIDTH-1:0] S_data2;
wire [2*WIDTH-1:0] F_mult;
reg clk;
initial begin
clk = 0;
S_data1 = 0;
S_data2 = 0;
#20;
S_data1 = 2;
S_data2 = 5;
#20;
S_data1 = 2;
S_data2 = 7;
#20;
S_data1 = 5;
S_data2 = 10;
#10;
S_data1 = 0;
S_data2 = 0;
#10;
repeat(30) @(posedge clk)
begin
S_data1[WIDTH-1:0] <= $random;
S_data2[WIDTH-1:0] <= $random;
end
end
always #5 clk <= ~clk;
mult_module
#(
.WIDTH(WIDTH)
)
mult_module_inst
(
.S_data1(S_data1),
.S_data2(S_data2),
.F_mult(F_mult)
);
endmodule
模擬: