AC620FPGA學習筆記——UART

• UART
• 硬體結構
• 整體框架
• 程式碼部分
• 頂層程式碼

UART

工程地址：https://github.com/HaHaHaHaHaGe/Planof2019_half/tree/master/Course_Project/FPGA/class05_UART
這是一個迴環測試專案，波特率115200 無校驗 1停止，傳入一個位元組回自動回傳同樣的一個位元組

硬體結構

開發板：AC620

整體框架

程式碼部分

程式碼過多更多程式碼在github

頂層程式碼

module top(
	clk,
	rst,
	tx,
	rx,
);

input clk,rst,rx;
output tx;
reg start;
wire busy;

wire [7:0]data;

reg rdreq;
reg wrreq;
wire empty,full;
wire [7:0]qout;
uart_tx uart_tx1(
	.clk(clk),
	.rst(rst),
	.start(start),
	.data(qout),
	.busy(busy),
	.tx(tx)
);


wire irq;
reg clr;
uart_rx uart_rx1
 
(
	.clk(clk),
	.rst(rst),
	.irq(irq),
	.data(data),
	.rx(rx)
);



fifo fifo1 (
	.clock(clk),
	.data(data),
	.rdreq(rdreq),
	.wrreq(wrreq),
	.empty(empty),
	.full(full),
	.q(qout)
);


reg [3:0]flag;
reg irq2;

reg flag2;
[email protected](posedge clk,negedge rst)
if(!rst) begin
	wrreq <= 0;
	flag2 <=
 
 0;
end
else case(flag2)
	0: if(irq) begin flag2 <= 1; wrreq <= 1; end else flag2 <= 0;
	1:begin wrreq <= 0; if(irq == 0) flag2 <= 0; end
endcase
	
	
[email protected](posedge clk,negedge rst)
if(!rst) begin
	start <= 1'b0;
	clr <= 0;
	flag <= 4'b0;
	rdreq <= 0;
end
else 
case(flag)
		0: if(empty == 0) begin rdreq <= 1; flag <= 1; end else flag <= 0;
		1: begin rdreq <= 0; flag <= 2; start <= 1; end
		2: begin start <= 0; flag <= 3; end 
		3: if(busy == 0) flag <= 0;
endcase
	


endmodule