RISC-V 雙週簡報 (2018-07-20)

要點新聞：

• 上海市經信委釋出RISC-V相關支援政策
• ARM F.U.D. 後續報道以及各方迴應

頭條

上海市經信委釋出RISC-V支援政策

上海市經濟資訊委最近釋出了《上海市經濟資訊化委關於開展2018年度第二批上海市軟體和積體電路產業發展專項資金（積體電路和電子資訊製造領域）專案申報工作的通知》，開始將從事RISC-V相關設計和開發的公司作為扶持物件，這也是國內第一個和RISC-V相關的扶持政策，說明上海市政府認可RISC-V的先進性、開放性以及逐漸完善的生態。

企業首先要是在上海註冊成立的，其次要以專案制的形式根據專案指南向上海市經信委政府提出申請，同時滿足一系列其他條件。

以下摘抄自《通知》的附件《2018年第二批上海市軟體和積體電路產業發展專項資金（積體電路和電子資訊製造領域部分）專案指南》:

5、基於RISC-V指令集架構的處理器晶片方向。

支援基於RISC-V指令集架構、32位及以上的處理器晶片的研發及產業化，核心需擁有自主智慧財產權。

• 方向一：面向物聯網和工控應用領域，具有優異的效能、功耗、面積等指標，優先支援有明確使用者合作協議的專案。專案執行期內累計銷售收入不低於2000 萬元。
• 方向二：面向智慧終端應用領域，主頻不低於1GHz，效能不低於1.5 DMIPS/MHz，支援雙精度浮點運算，支援主流作業系統、多核技術及快取一致性。專案執行期內累計銷售收入不低於1000 萬元。

行業視角

EETime: Is This the Moment for RISC-V?

EETime最近發表文章"Is this the moment for RISC-V?"，文章提到了RISC-V在中國和印度的發展。

Sherwani commented that there are some 300 companies already looking at or developing with RISC-V in China. Rupert Baines, CEO of UltraSoC, said to EE Times that there’s huge innovation going on in China and that the drive for the architecture and products will more likely come from China than India. He has a point — India has been talking about its development of a RISC-V processor, the Shakti processor, for some time, as Rick Merritt wrote two years ago.

同時也提到了印度大量人才都轉向了處理器和EDA工具的開發，而且這也是有歷史原因的。

India does indeed have a strong background in advanced electronics and computing, but somehow its talent was in the early days diverted to becoming part of the offshore development teams for many of international semiconductor and EDA companies. The country’s ecosystem and engineers already have over 30 years of experience in developing electronics systems and processors. Texas Instruments first established a design center in Bangalore in 1985, and engineers there have worked on several DSPs and application specific products, including its first DSP for automotive in 1995, and various DSP cores and mixed signal ASICs, including 3G wireless chip set designs back in 2000.

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RV新聞

Chennai Workshop成功舉辦

緊隨著Shanghai Day，7月16日，RISC-V Workshop在印度金奈舉辦，為期兩天的Workshop內容非常豐富。

其中InCore Semiconductor，也就是Shakti專案孵化出的公司表現比較搶眼，大家可以著重去看看他們的Slides，

InCore Semiconductor is founded by members of the Shakti Research team to create commercial RISC-V solutions leveraging the Shakti Open Source IP and research efforts.

Focus is on AI/ML, Security, IoT Wireless and Fault Tolerant applications.

InCore的路線圖中，除了3級流水和5級流水的通用核以外，支援高可靠、容錯和Lock-step的核心也在其版圖範圍內。

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ARM F.U.D. 後續報道以及各方迴應

來看看業界對於ARM前端時間發起的業界普遍認為是典型的F.U.D.行為的後續報道和業界的迴應。

先來看看什麼是F.U.D.(Fear, Uncertainty, Doubt)，它最早指IBM銷售人員對客戶灌輸阿姆達爾公司和其他競爭對手產品的負面觀念，在顧客的頭腦中注入疑惑與懼怕，使顧客誤以為除了該公司的產品外，他們別無其他選擇。兩千年左右Microsoft對Linux也做過類似的事情。

根據The Register的報道，ARM內部員工似乎對這樣的宣傳手段產生了分析和不認同，隨後該網站被關閉。

RISC-V基金會主席在EETime上發表文章，非常溫柔的迴應了arm的5條置疑(中文翻譯來自eettaiwan)：

RISC-V has the potential to cut processor licensing costs, but more importantly gives customers the freedom to choose. An open architecture enables competition between open-source implementations, home-grown implementations and commercial pre-verified implementations with professional support.

RISC-V具備能削減處理器授權成本的潛在能力，但更重要的是提供客戶選擇的自由。一個開放性架構能促成開放原始碼設計成果、自產設計成果，以及具備專業支援的商業化預驗證設計成果之間的競爭。

The RISC-V ecosystem is relatively young, but growing far more rapidly than any previous ISA. The RISC-V ecosystem would have taken far longer to advance to its current state without the high-quality open-source compilers, operating-systems and debug tools used by all architectures that were quickly ported and up-streamed by the open-source community. In addition to the broad range of open-source tools, there are an increasing number of professional development tools from established industry leaders being ported to RISC-V in response to customer demand.

RISC-V生態系統相對較年輕，但成長速度高於任何一種過去的ISA。而若不是有適用於所有架構的高品質開放原始碼編譯器、作業系統與除錯工具RISC-V，能快速移植並讓開放原始碼社群納入上層(up-stream)，RISC-V生態系統可能要花更長的時間才能進展到目前的狀態。除了廣泛的開放原始碼工具，也有廠商推出越來越多支援RISC-V的專業開發工具，以因應客戶需求。

RISC-V was designed to support specialization while avoiding fragmentation by mandating a frozen common ISA standard around which the software community coalesces, while leaving ample space for innovative custom extensions that do not interfere with standard instructions and the standard software stack.

RISC-V的宗旨在於支援專門化(specialization)，同時藉由授權一個軟體社群所聚集的、凍結的常用ISA標準避免多頭髮展(fragmentation)，同時為不干擾標準指令與標準軟體堆疊的創新客製化延伸留下足夠空間。

Security is perhaps the greatest challenge in modern computer architecture and existing proprietary security architectures have clearly failed, as is evident from wave after wave of published attacks. RISC-V provides perhaps the best hope for developing effective security architectures.

安全性或許是現代電腦架構面臨的最大挑戰，而現有的專屬安全架構顯然已經失敗──有鑑於層出不窮的駭客攻擊事件曝光；RISC-V能為開發有效的安全架構帶來最大希望。

The ISA is simple and amenable to formal verification. The free and open license allows implementations to be audited by external experts. The security research community has embraced RISC-V, and there are already several commercial secure RISC-V core implementations. Several governments are investing heavily in RISC-V because they can develop their own trusted secure cores without relying on foreign IP, but while still maintaining compatibility with the RISC-V software ecosystem.

此種ISA的形式化驗證(formal verification)簡單易行，免費與開放性授權讓各種設計實作能透過外部專家稽核；安全性方案研發社群已經採用了RISC-V，而且已經有很多商用安全性RISC-V設計成果。有多國政府也正在大舉投資RISC-V，因為能在不需仰賴外國IP的情況下開發他們自己的可信任安全核心，同時維持與RISC-V軟體生態系統的相容性。

The free and open license terms have enabled a rapid proliferation of open-source RISC-V cores and a rapidly growing commercial RISC-V soft-core industry. Multiple companies that are foundation members are supplying high-quality pre-verified cores and professional support. RISC-V already has far more commercial soft-core suppliers than any other ISA, all compatible with a single standard.

免費、開放的授權條款，讓開放原始碼RISC-V核心快速繁殖，也讓商用RISC-V軟核心市場快速成長；有多家身為基礎成員的公司正在提供高品質的預驗證核心以及專業支援，RISC-V已經擁有比其他ISA更多的商用軟核心供應商，而且都相容於單一標準。

Freedom to innovate and collaborate is critical to our industry’s future, and will enable hardware to become a vibrant partner following software’s lead in creating trailblazing new products. We welcome all to join us in the open hardware revolution.

自由地創新以及合作對產業的未來至關重要，也將使得硬體成為活躍的夥伴，追隨軟體的腳步打造新產品；我們歡迎所有人加入開放性硬體革命的行列！

而由某個匿名者發起的arm-basics.com網站也隨著ARM FUD網站的關閉而於最近關閉。arm-basics.com最有趣的地方在於網站完全執行在Github上，從一個空白的網頁，通過網友不斷的提交Pull Request來完善其內容，以一種開源和開放的方式有力的迴應了Arm的指責。

以下是根據Github上的存檔，網站上反駁ARM的六點。

Six things to consider before designing a System-on-Chip

The instruction set architecture (ISA) is the foundation of all chip or System-on-Chip (SoC) products. It is therefore one of the most fundamental design choices you will make. If you are considering using a proprietary ISA, such as ARM, it is critical to understand the key factors you should consider as part of your go-to-market strategy.

Cost

Proprietary instruction set architectures, such as ARM, have a license fee and currently an ongoing royalty model that can cost tens of millions of dollars. Moreover, the cost of licensing an ARM ISA accounts for at least 1% of all your sales.

ARM annual architectural license fee pays for complete design team for several RISC-V cores.

Fragmentation risk

ARM fragments their own ISAs (ARM v6/7/8, Thumb 1, Thumb2, ThumbEE, Jazelle, ARM v8, v8-M, NVIC/VIC/GICv2/3/4, multiple hypervisor variants/…, DSP/NEON/VFP/SVE).

ARM doesn’t allow users to customize, forcing them to buy a second core, or more wisely, move to RISC-V.

Improvements

The ARM instruction set architecture doesn’t allow open-source developers to contribute. This means you are stuck at the mercy of the original vendor and any backdoors it might have. This restriction makes it more difficult for people to trust your chip and prevents the community from bringing improvements to your systems for free.

Design Assurance

Verification and validation of processor designs can consume 75% of total design time. Having it open source means volunteers can participate in the creation of your design by bringing their unique expertise in the field, for free. This reduces design costs.

Extensions are optional, you can buy preverified cores. In fact, 8x fewer instructions and simpler privilege architecture results in a much simpler verification process.

Large, Supportive Community

It is important an architecture is well received by an active community, so it can help you port a more diverse range of software, services and designs to your processor architecture. This guarantees market choice, product quality and an optimal time to market. Proprietary ecosystems do not have this level of trust and openness.

It’s true RISC-V ecosystem is weaker than ARM’s right now, but it is growing much faster.

Security

Cyberthreats mean that robust chip security cannot ever be optional. Proprietary products can be severely insecure, and because they can’t benefit from years of scrutiny from open source developers and industry experts, Spectre and Meltdown can happen to them. ARM doesn’t concern itself with security issues as the public expects. They ignored ret2usr for a very long period of time, while millions of ARM users were exposed to the massive exploit, until a few security features (domain, PXN) were added into ARMv7. The 1st PXN implementation was done by PaX/Grsecurity, while the 1st implementation of domain was done by PaX’s UDEREF. To date, ARM has yet to credit them. RISC-V will have the chance to make things right in the beginning and that’s what security subgroups and Security Standing Committee from the RISC-V foundation have been doing from the start.

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技術討論

39 位的指令虛擬地址寬度已經夠寬的了

Peter J Smith 在 RISCV ISA Dev 的郵件列表裡提出建議，指令的虛擬地址寬度保持 39位足矣，甚至位數可以更少；而資料的虛擬地址可以用到 48 位寬的。指令和資料的地址空間沒有必要一樣，一般來說指令的地址空間只會非常小。隨著訪問的資料越大，消耗在指令虛擬地址轉換上的硬體資源就越多（資料、指令的虛擬地址寬度一致，但指令用到的空間不多）。他認為應用程式不會用到這麼多的指令虛擬地址空間。

David Chisnall 迴應到，他想到兩個需要比較大的指令虛擬地址空間的使用例子：

1. 如果需要做類似 ASLR 的事情，限制指令虛擬地址空間會降低隨機性（熵）。程式碼地址必須在按頁對齊的塊裡，也經常在父頁（superpag-aligned）對齊的塊裡。對於 2MB 的 spuerpages（SV48），需要花費 20 bits 用於底部，因此留下19位用於隨機化（熵），這樣探測出來需要的成本低。

2. 對於CHERI 型別的單個地址空間劃分，甚至 48 位都不太夠。每個劃分保留 4GB，48 位的話只有分成 64K 個，這對於大多數的 UNIX 系統使用的 PID 空間小得多。也就是說，他不認為資料和程式碼的虛擬地址空間非要一致以及對於任何特定的微體系結構進行解耦它們是有意義的。

對於這點指令的虛擬地址寬度，39 位是否已經足夠的更多看法，可以參見郵件列表: isa_dev

Custom instructions (如何新增自定義指令到risc-v中)

riscv-opcodes wasn’t added to FSF binutils, so it not being used to maintain the assembler/disassembler, though I don’t know if it was ever used for that. The info in this URL looks OK. And the fact it works for mod seems to indicate that it is OK. if it isn’t working for your mac instruction then maybe you made a mistake.

Actually, looking at this again, I see you want an instruction with 3 inputs, but are using an instruction format that only supports 2 input registers. Maybe compiler optimization is changing the destination register, which is breaking your attempt to use the destination register as an input. You also need to modify the asm to indicate that the destination is also an input. You can do this by changing

: [z] "=r" (c) to : [z] "+r" (c)

However, it would be best if you used an instruction format that properly supports 3 input registers to avoid confusion. See for instance the fmadd instructions, though since you want to do this for an integer instruction, you will need more changes to add operand description letters for a third input, which will require gas/config/tc-riscv.c changes.

it is probably easier is you just use .insn instead.

大意是repo: riscv/riscv-opcodes的指令還沒有upstream到binutils中，所以binutils的維護者FSF過去沒有持續維護彙編器和反彙編器關於RISC-V指令功能。

arup de新增的是一個三輸入指令，但是參考的是已有的兩輸入指令修改的, 最好是是參考比如fmadd這樣的三輸入指令來修改。

Sathya Narayanan N給出了詳細完全的指導:

1. Go to riscv-tools/riscv-opcodes/opcodes. All the instructions will be written there in a specific format. The format will also be mentioned in the file. Instructions will also be grouped together in a specific logic. Choose which logic is more suitable for the custom instruction and then add it to that group. For example, the instruction added is ‘ctz’, it can be.

   在riscv-tools/riscv-opcodes/opcodes包括了risc-v現在支援的所有指令，而且被分門別類的整理好了。 你從中找一個跟你新新增的指令最適合的指令來參考新增你的自定義指令。

2. Then, run the following command from the riscv-opcodes folder terminal to obtain the match and mask code.

   通過下面命令把新增的指令生成相關的程式碼,並儲存在temp.h中

   cat opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom | ./parse-opcodes -c > <path name>/temp.h

3. Go to the temp.h and copy the match and mask code.

   開啟temp.h並複製程式碼

4. Paste the match and mask code in the

   把程式碼貼上到

   riscv-gnu-toolchain/riscv-binutils-gdb/include/riscv-opc.h

5. Then, the instruction is initialised by going to

   然後在下面檔案中初始化你的指令 riscv-gnu-toolchain/riscv-binutils-gdb/opcode/riscv-opc.c

The constructors have various parameters such as type of instruction (I for immediate and C for compressed) and operands, where in most cases, the variables given will be d(destination), s(source), t(transition).

構造方法中有很多引數，包括指令的型別(比如I為立即數，C為壓縮指令), 運算元。運算元可能是目標數，源運算元，中間傳遞暫存器

同時Sathya Narayanan N也提到RISC-V不但支援三運算元指令，也支援四運算元指令

p.136 (table 22.2) v2.3-draft risc-v isa manual shows you some of the types of standard instructions (and p134 shows more). one of them is called “R4 type”. so the answer’s yes.

Rocket-chip裡DecodeLogic的工作原理

Liwei(david mlw)在HW-Dev郵件組提到了關於Rocket晶片程式碼的疑惑: DecodeLogic()函式分別在idecode.scala和fpu.scala以不同的方式被呼叫。在DecodeLogic的原始定義中（參看decode.scala）, 返回值是UInt型別的系列。但在idecode.scala和fpu.scala的呼叫裡，返回值卻是不一樣的。這是如何做到的呢？

在idecode.scala

def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {
   val decoder = DecodeLogic(inst, default, table)
   val sigs = Seq(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2,
                  sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type,
                  rfs1, rfs2, rfs3, wfd, mul, div, wxd, csr, fence_i, fence, amo, dp)
   sigs zip decoder map {case(s,d) => s := d}
   this
}

在fpu.scala

val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
               s.swap23, s.singleIn, s.singleOut, s.fromint, s.toint,
               s.fastpipe, s.fma, s.div, s.sqrt, s.wflags)
sigs zip decoder map {case(s,d) => s := d}

Chris提供的答案是，DecodeLogic呼叫Quine-Mccluskey演算法(注：一種布林函式最小化的簡化方法)執行邏輯最小化，將一組鍵值對映到輸出訊號，其中輸入表允許使用0,1和dontCare。更詳盡的解釋是instructions.scala定義了指令模式，Decode中的表是從指令到結果訊號的對映，而DecodeLogic優化了對映邏輯。之所以idecode.scala和fpu.scala得到不同的結果，是因為它們輸入不同的表。

另外，Ed提出了一個有趣的問題: 像DecodeLogic這樣的預先簡化控制邏輯是否比直接使用邏輯綜合工具（synthesis tool）更好的結果？是不是Chisel工具本身還有限制，讓生成的"always" blocks還沒辦法讓邏輯綜合工具（synthesis tool）在現階段進行很好的優化？

對於這個問題，Chris的回答是，在Chisel中，我們避開了語言中1’hx的使用（除了一些非常有限的特例外）。因此，我們不能在常規case語句中提供1’hx，沒法讓verilog工具做優化。

理解（Return Address Stack）RAS （push）推棧和（pop）彈棧的用例

Pierre G. 提出了自己對於 RISC-V 指令集手冊 卷 1:使用者級指令集體系結構 2.2 版中對於 表 2.1: 在指令中將返回地址棧預測暗示編碼進暫存器的分類使用 的理解，並提出了自己對於“ push and pop ” 的疑惑。

背景資訊：

間接跳轉指令 JALR(jump and link register) 使用I類編碼。通過將 12 位有符號 I 類立即數加上 rs1, 然後將結果的最低位設定為0, 作為目標地址。跳轉指令之後的指令地址 (pc + 4) 儲存到暫存器 rd 中。

rd	rs1	rs1=rd	RAS action
!link	!link	-	none
!link	link	-	pop
link	!link	-	push
link	link	0	push and pop
link	link	1	push

Samuel Falvo II 糾正了他的觀點：

1. RAS 是實現細節和一種優化手段，通過主分支的預測邏輯以加速子程式的呼叫和返回。執行 JAL® 時並不影響對暫存器 Rd 的更新，如果預測失敗，核心將必須跳入 Rs1 + imm。
2. 立即數總是有用的。
3. 當對 RAS 做彈棧操作的目的是預測返回地址。如，在取指階段獲取 RAS 頂的地址，並希望這是對的。但有可能猜錯，這僅在 Rs1+imm == RAS 的 top (棧頂) 時，則JALR 實際執行了，才算預測正確。否則，必須清流水線，從 Rs1+imm 重新取指。
   • 有四種典型的棧操作： Push， Pop ，Push & Pop； Peek 是一個非破壞性棧頂讀操作。

Cesar Eduardo Barros 也確認了以下觀點：

1. JALR 對於 RAS 是有影響的，但是 RAS 不影響 JALR。
2. RAS 基本上是一種優化，處理器試圖從 RAS 中獲得下一指令地址(預測)，並在得到真正地址時進行確認，若猜錯，需重新取指。
3. 這種優化程度有限，並有被黑客利用風險。
4. Spike 模擬器沒有 RAS 實現，因為對於模擬器，這種優化沒有必要。

Rogier Brussee 詳述了 “CALL ra imm32”虛擬碼的具體實現並指出了其改進過程

auipc ra hi(imm32)
jalr ra ra lo(imm32)

同時貼出了對於以下兩行程式碼的執行效率的討論：

jalr ra t0 lo(imm)
jalr t0 ra lo(imm)

程式碼更新

Renode 1.4支援基於RISC-V的平臺

小編和你們一樣不瞭解Renode是啥，簡言之，Renode是一個快平臺的模擬開發框架，能夠在本地模擬外設等，而執行在這個平臺上的應用可以無縫交付到多個基於Renode的平臺上，包括基於Linux和基於Zepyher的。

Renode最近開始支援HiFive1和HiFive Unleashed平臺。

市場相關

AndesTech最近營收中RISC-V佔4成

根據最新的報道，臺灣晶心科技最近的營收有創新高，而且RISC-V相關的License Fee佔到了4成。

去年底晶心科推出採RISC-V架構推出N25、NX25兩款新方案，今年晶心科再推N25F、NX25F、A25、AX25四款新品。晶心科表示，6月營收當中，當中有4成是RISC-V貢獻，並且集中在AI的應用面。

小編：短短几年時間就取得如此成績，從側面說明了AndesTech選擇擁抱RISC-V是非常正確的決定，而RISC-V也因有了AndesTech而更加強大，形成雙贏的局面。

暴走事件

2018年8月

• 2018年8月15日-18日在寧夏大學舉辦的計算機工程與工藝學術年會及第八屆“微處理器論壇”中，會有一場關於“RISC-V開放指令集和其硬軟體生態”的大會報告。

2018年10月

• 2018年10月18日, RISC-V Day Tokyo將在Keio University舉辦，演講徵集已經開始。註冊網站

2018年12月

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