//級聯BCD計數器設計與模擬
module cy4(Cin,CLK,Rst_n,Cout,q);
input Cin;//計數基準時鐘
input CLK;//計數器進位輸入
input Rst_n;//系統復位
output q;//技術值輸出
output Cout;//計數器進位輸出
wire Cout0,Cout1;
wire[3:0]q0,q1,q2;
wire[11:0] q;
assign q = {q2,q1,q0};



BCD BCD_Cout0(
      .CLK(CLK),
	  .Cin(Cin),
	  .Rst_n(Rst_n),
	  .Cout(Cout0),
	  .q(q0)
	  );
BCD BCD_Cout1(
      .CLK(CLK),
	  .Cin(Cout0),
	  .Rst_n(Rst_n),
	  .Cout(Cout1),
	  .q(q1)
	  );
BCD BCD_Cout2(
      .CLK(CLK),
	  .Cin(Cout1),
	  .Rst_n(Rst_n),
	  .Cout(Cout),
	  .q(q2)
	  );	
endmodule	  


module BCD(CLK,Rst_n,Cin,Cout,q);
input CLK;
input Rst_n;
input Cin;
output reg Cout;
output q;
wire [3:0]q;
reg[3:0] cnt;


always @(posedge CLK or negedge Rst_n)
if(!Rst_n)
cnt <= 4'd0;
else if(Cin == 1'b1)begin
if(cnt == 4'd9)
  cnt <= 4'd0;
else cnt <= cnt + 1'b1;
end
else
    cnt <= cnt;
	
always @(posedge CLK or negedge Rst_n)
if(!Rst_n) Cout <= 1'b0;
else if(Cin == 1'b1 && cnt == 4'd9)
         Cout <= 1'b1;
else Cout <= 1'b0;

assign q = cnt;

endmodule

 

測試指令碼程式碼

`timescale 1 ns/ 1 ps
`define clock_period 20
module cy4_vlg_tst();
reg CLK;
reg Cin;
reg Rst_n;                                              
wire Cout;
wire [11:0] q;
                       
cy4 i1 ( 
	.CLK(CLK),
	.Cin(Cin),
	.Cout(Cout),
	.Rst_n(Rst_n),
	.q(q)
);
initial CLK = 1'b1; 
always #(`clock_period/2)CLK = ~CLK; 
initial                                                
begin                                                  
Rst_n = 1'b0;
Cin = 1'b0;
#(`clock_period*200);  
Rst_n = 1'b1; 
#(`clock_period*20);  
Cin = 1'b1;    
#(`clock_period*5000);  
$stop;                                   
end                                                    
endmodule