The Microprocessor and Its Architecture

mode

Register

General-Purpose Registers / Multipurpose Registers

• RAX (accumulator)

  • 低位改變不影響高位
  • 通常用於儲存**乘數、除數、adjustment instructions、地址偏移

• RBX (base index)

  • 有時用於儲存偏移地址

• RCX (count)

  • 也可以儲存地址
  • 涉及迴圈、計數的命令用RCX

REP/REPE/REPNE
LOOP/LOOPD

• RDX (data)

  • 乘法的積、除法的商
  • 也可以儲存地址

• RBP (base pointer)

  • 指向記憶體地址

• RDI (destination index)

  • 字元命令目標地址

• RSI (source index)

  • 字元命令源地址

• R8 - R15

  • 只能用右邊的n位：R8B,R8W,R8D,R8

Special-Purpose Registers

• RIP(instruction pointer)

64位，40位匯流排，1T扁平地址空間

• RSP(stack pointer)

• RFLAGS / EFLAG / FLAG

  • C(carry):加法進位、減法借位
  • P(parity):奇偶校驗，數有幾個1
  • A(arxiliaty carry)?
  • Z(zero)
  • S(sign):正負數，指示最高位的0或1
  • T(trap):用來debug的
  • I(interrupt):是不是允許中斷
  • D(direction0):1 – 自減；0 – 自加
  • O(overflow):加減溢位
  • IOPL(I/O privilege level):00最高，11最低
  • NT(nested task)？
  • RF(resume):除錯用
  • VM（virual mode):在Windows系統下模擬DOS（我自己也不知道這是啥）
  • AC(algnment check)?
  • VIF(virtual interrupt)
  • VIP(virtual interrupt pending)
  • ID(identification): CPUID

• Segment Rigisters

  • CS(code):程式碼段起始地址
  • DS(data):the beginning of the data segment
  • ES(extra): some of the string instructions to hold destination data
  • SS(stack): the beginning of the stack segment
  • FS and GS: allow two additional memory segments with no definition of usage

Program Invisible Registers

• purpose: access the address of descriptor tables

• cache(program-invisible portion of the segment registers): each time the content of the segment registers changes the microprocessor would get the corresponding descriptors and place it into the cache

• GDTR / IDTR(global / interrupt descriptor table register): address and limit(16-bit)

• TR(task register): store a descriptor to describe a procedure or application program

Mode

8084,8088: real mode – first 1M(real memory, conventional memory, DOS memory)

80286 and above: real or protected

Pentium 4 and Core2: no real mode operation

segment

all real mode memory address must consist of a segment address plus an offset address

• segment size – 64KB(16 bits)
• each segment register is internally appended with a 0H on its righmost end – 20 bits address – a segment can start at any location
• high memory(0FFFF0H - 10FFEFH): for driver for DOS ---- (64K-16)B
• modulo ---- control the addresses available within the area of a segment

Defalut Segment and Offset Register

• CS:IP
• SS:SP / SS:BP
• DS:BX/DI/SI/direct number
• ES:DI

in real mode, only the rightmost 16 bits of the extended register address a location within the memory segment, meaning that no larger than 64KB

Protected Mode

• Windows uses protected mode
• inside and outside the first 1MB
• the difference lies in :
  1. the way that the segment register is interpreted by the microprocessor
  2. 16-bit offset -> 32-nit offset

Selectors and Descriptors

• two tables – each 8196 descriptors
• global descriptor / system descriptor
• local descriptor / application descriptor
• format
  • base address – 24 bits / 32 bits(80386 and above)
  • limit – 16 bits / 20 bits(80386 and above) – the offset of the last address in the segment
  • G ---- if G=1, then the segment size becomes 4GB and the step becomes 4KB (means multiplied by 4K/limit <- limit FFFH)
  • L ---- L=1 -> 64-bit extension / L=0 -> 32-bit compatibility mode
  • AV ---- available(1) or not(0)
  • accress rights byte — growth direction, write accress …(note:64-bit mode only has code segment)

Flat Mode Memory

• CS – descriptor
• only code segment

Segment Register in Protected Mode

• selector – 13 bits – choose descriptor
• TI — global(0), local(1)
• RPL(requested privilege level) — 11最低 — 於segment privilege level比較進行訪問控制

Memory Paging

Paging Registers (operating system)

• provide 2G linear address space, no matter there is enough or not

CR0

• PG – 1->paging;0-> no paging

CR3

• PWT ?
• PCD ?

address format

• page directory entry
• page table entry
• memory page offset address
• TLB(translation look-aside buffer)