剛開始學習verilog，自己寫了個密碼鎖，看上去有不少bug，不過在老師那裡過關了，是自己的第一個獨立完成的verilog程式，試著發個部落格記錄下，同樣也是第一次發部落格。

     下面貼程式碼，先是消抖部分：

module mimasuo(clk,key_in,led,rst,led_test);
input clk;
input [3:0] key_in;
input rst;
output [2:0]led;
output [2:0]led_test;
reg [23:0] count;
reg [3:0] key_scan;
[email protected](posedge clk or negedge rst)
begin
    if(rst)
        count <= 24'd0;
    else begin
    if(count == 24'd3999999)
        begin 
            count <= 24'b0;
            key_scan <= key_in;
        end
        else
            count <= count + 24'b1;
          end
end

reg [3:0] key_scan_r;
 
[email protected](posedge clk)
    key_scan_r <= key_scan;
    wire [3:0] flag_key = key_scan_r[3:0] & (~key_scan[3:0]);

reg [3:0] ouut;
[email protected](posedge clk or negedge rst)
begin
    if(rst)
    ouut <= 4'b0000;
    else begin if(flag_key[0])
        ouut[0] <= 1;
        if(flag_key[1])
                ouut[1] <= 1;
        if(flag_key[2])
                ouut[2] <= 1;
        if(flag_key[3])
                ouut[3] <= 1;
        end
end 
reg [2:0] led_temp;
reg [32:0] cnt;
reg [2:0] led_test_output; 
parameter s0 = 3'd7,s1 = 3'd6,s2 = 3'd4,s3 = 3'd0,s4 = 3'd5;  
 
[email protected] (posedge clk)
begin
    if(rst)
    begin
    led_test_output <= 0;
    led_temp <= s0;
    cnt <= 0;
    end
    else begin if(ouut[0])
        begin 
            cnt <= cnt +1;
            if (cnt == 32'd199999999)
                begin    
                    led_temp <= s4;
                    cnt <= 0;
                end
            else
                begin 
                    case(led_temp) 
                        s0:begin
                            if(ouut[1])
                                begin
                                    led_temp <= s1;
                                end
                            else
                                begin
                                    led_temp <= s0;
                                end
                           end
                         s1:begin
                            if(ouut[2])
                                begin
                                    led_temp <= s2;
                                end
                            else
                                begin
                                    led_temp <= s0;
                                end
                           end
                        s2:begin
                            if(ouut[3])
                                begin
                                    led_temp <= s3;
                                end
                            else
                                begin
                                    led_temp <= s0;
                                end
                            end
                         s3:begin
                            if(flag_key[1]) led_test_output[0] <= ~led_test_output[0];
                            if(flag_key[2]) led_test_output[1] <= ~led_test_output[1];
                            if(flag_key[3]) led_test_output[2] <= ~led_test_output[2];
                            end
                         s4:begin 
                            led_temp <= s4;
                            end
                       endcase 
        end
            end
      end 
end  
assign led[0] = led_temp[0];
assign led[1] = led_temp[1];
assign led[2] = led_temp[2]; 
assign led_test[0] = led_test_output[0];
assign led_test[1] = led_test_output[1];
assign led_test[2] = led_test_output[2];                                                  
endmodule
 

module mimasuot;
    reg clk;
    reg [3:0]key_in;
    reg rst;
    wire [2:0]led;
    wire [2:0]led_test;
    mimasuo uut(
                .clk(clk),
                .key_in(key_in),
                .rst(rst),
                .led(led),
                .led_test(led_test)
                );
initial begin
    clk = 1;
    forever #25 clk = ~clk;
        end 
 
initial begin
    rst = 1;
    #100;
    rst = 0;
    key_in = 4'b0000;
    #100;
    key_in = 4'b0001;
    #200000000;
    key_in = 4'b0000;
    #10000;
    key_in = 4'b0010;
    #200000000;
    key_in = 4'b0000;
        #10000;
    key_in = 4'b0100;
    #200000000;
    key_in = 4'b0000;
        #10000;
    key_in = 4'b1000;
    #200000000;
    key_in = 4'b0000;
        #10000;
    key_in = 4'b0010;
        #200000000;
    key_in = 4'b0100;
        #200000000;
    key_in = 4'b0000;
    #200000000;
    $stop;
    end   
endmodule

模擬是用vivado自帶的模擬軟體做的，modelsim做需要斷網才行，這個問題試了好多辦法都沒解決，只好用vivado自帶的。這個是個比較簡單明瞭的程式，所以也沒寫什麼解釋，不過用來解決大作業足矣。

     後面準備學習DDR3和eMMC的除錯，這個就算是上手訓練吧。