verilog中支援signed 資料型別，即支援負數的處理。此時參與運算的各個數均應是signed型別，且資料位寬相同(若位寬不相同，則應手動將其擴充套件為位寬相同，具體做法就是將最高位的符號位進行擴充套件),且運算結果要比運算數的位數大以防止溢位。以下用兩個小例子進行說明。細節可參考此篇文章： http://www.cnblogs.com/oomusou/archive/2009/10/31/verilog_signed_overflow.html

Examp 1.

module top(clk,a,b,c);
       input clk;
       input signed [7:0]  a;
       input signed [7:0]  b;
   output reg signed [8:0] c;                               
 
   
 
[email protected](posedge clk)
     begin
      if((a-b)< 0)
         c <= b - a;
      else if ((b-a)==0)
         c <= 0;
      else
          c <= a - b;
     end
     
endmodule

module sim_top ;

        reg clk;
        reg signed [7:0]  a;
        reg signed [7:0]  b;
       wire signed [8:0] c;

initial begin
clk= 0;
a=0;
b=8;
forever clk=#5 ~clk ;
end

 
[email protected](posedge clk)
     begin
      a<=a+2;
      b<=b+1;
     end

    top my_top(
     .clk(clk),
     .a(a),
     .b(b),
     .c(c));

endmodule

Examp 2：

module top(clk,a,b,c);
       input clk;
       input signed [7:0]  a;
       input signed [7:0]  b;
   output reg signed [8:0] c;                               
 
   
 
[email protected](posedge clk)
     begin
     /* if((a-b)< 0)
         c <= b - a;
      else if ((b-a)==0)
         c <= 0;
      else*/
          c <= a - b;
     end
     
endmodule

模擬結果：