【FPGA】【Verilog】【基礎模組】3-8譯碼器
阿新 • • 發佈:2019-02-19
使用移位實現:
module decoder(out ,in);
output [7:0 ] out ;
input [2:0] in;
assign out = 1'b1 << in;
endmodule
使用case實現:
module decoder1(out,in); output [2:0] out; input [7:0] in; reg [2:0] out; always @(in) begin case (in) 3'b000: out <= 8'b0000_0001; 3'b001: out <= 8'b0000_0010; 3'b010: out <= 8'b0000_0100; 3'b011: out <= 8'b0000_1000; 3'b100: out <= 8'b0001_0000; 3'b101: out <= 8'b0010_0000; 3'b110: out <= 8'b0100_0000; 3'b111: out <= 8'b1000_0000; default:out <= 8'bz; endcase end endmodule