在FPGA中使用Verilog實現I2C通訊
按照I2C標準的官方時序
可以看出時序看起來很簡單，不過它嚴格的按照時序要求來傳送資料，馬虎不得的，特別是起始和停止的條件，起始必須要時鐘線SCL為高電平時資料線SDA拉低；而停止時必須要時鐘線SCL為高電平時資料線SDA拉高；中間的資料的每一位傳送都是必須要求在時鐘線SCL為高定平時完成；
Verilog HDL程式採用基於狀態機的時序設計實現，I2C速度為100KHz，本人開發板的晶振20Mhz。程式碼有點長，就擷取狀態機部分好了
`define DEVICE_WRITE 8'b1010_1010 //the data;
reg[7:0] db_r;
parameter IDLE = 4'd0;
parameter START1 = 4'd1;
parameter DATA = 4'd2;
parameter ACK1 = 4'd3;
parameter STOP1 = 4'd11;
parameter STOP2 = 4'd12;
reg[3:0] cstate;
reg sda_r;
reg sda_link;
reg[3:0] num;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
cstate <= IDLE;
sda_r <= 1'b1;
sda_link <= 1'b0; //input
num <= 4'd0;
end
else
case (cstate)
IDLE: begin
sda_link <= 1'b1; //output
sda_r <= 1'b1;
db_r <= `DEVICE_WRITE;
cstate <= START1;
end
START1: begin
if(`SCL_HIG) begin
sda_r <= 1'b0;
cstate <= DATA;
num <= 4'd0;
end
else cstate <= START1;
end
DATA: begin
if(`SCL_LOW) begin
if(num == 4'd8) begin
num <= 4'd0;
sda_r <= 1'b1;
sda_link <= 1'b0; //(input)
cstate <= ACK1;
end
else begin
cstate <= DATA;
num <= num+1'b1;
case (num)
4'd0: sda_r <= db_r[7];
4'd1: sda_r <= db_r[6];
4'd2: sda_r <= db_r[5];
4'd3: sda_r <= db_r[4];