AXI介面的MIG測試【MIZ7035學習】
1.前言
剛買了米聯客的MIZ7035開發板，這幾天休假也不出去，就在家拿回來測一些東西。
主要目的是學習：
PL端的DDR3介面
GTX用作PCIE介面
SFP介面
HDMI介面
SD卡和eMMC共存情況下的PetaLinux
主要就是這些了。過程主要是自己根據原理圖、文件在Vivado上直接新建工程來進行測試，米聯客的資料作為輔助，需要時進行檢視。
這次先來測試MIG做出的DDR3控制器，看看效果怎麼樣。
2.新建Vivado工程
新建工程，點選Next
選擇FPGA型號
點選Next，Finish
新建BD,點選OK
3.AXI介面的MIG IP
點選Add IP，新增MIG IP
雙擊MIG IP的GUI,
彈出視窗Xilinx Memory Interface Generator，
點選Next
預設新建設計，1個控制器，AXI4介面
點選Next
選擇DDR3 SDRAM
預設設定800MHz時鐘，然後修改Memory Part為MT41K256M16XX-125，Data Width選擇32位，其他設定預設
AXI的Data Width選擇64位和PS的HP介面對應或者32位和GP介面對應，地址線讀寫仲裁選擇ROUND_ROBIN，其他預設
因為剛才選了800MHz和4:1，所以這裡的輸入時鐘選擇200MHz，其他預設
系統時鐘和參考時鐘來源於FPGA內部，這裡選擇No Buffer，其他預設
內部終端電阻選擇50歐
板子已經是現成的選擇Fixed Pin Out
參照原理圖，填寫所有引腳的資訊，然後點Validate驗證。或者直接讀取建立好的UCF檔案。
UCF內容：
NET "ddr3_dq[0]" LOC = "G1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[1]" LOC = "J4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[2]" LOC = "H1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[3]" LOC = "H4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[4]" LOC = "H2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[5]" LOC = "L3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[6]" LOC = "J1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[7]" LOC = "K3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[8]" LOC = "F3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[9]" LOC = "C1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[10]" LOC = "E2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[11]" LOC = "D3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[12]" LOC = "G4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[13]" LOC = "D1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[14]" LOC = "E1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[15]" LOC = "F4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[16]" LOC = "M1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[17]" LOC = "L5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[18]" LOC = "M4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[19]" LOC = "M5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[20]" LOC = "M2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[21]" LOC = "N4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[22]" LOC = "L2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[23]" LOC = "N1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[24]" LOC = "K6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[25]" LOC = "K7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[26]" LOC = "N7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[27]" LOC = "J5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[28]" LOC = "M7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[29]" LOC = "K8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[30]" LOC = "N6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[31]" LOC = "K5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dm[0]" LOC = "H3" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dm[1]" LOC = "D4" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dm[2]" LOC = "M6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dm[3]" LOC = "J6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[0]" LOC = "K2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[0]" LOC = "K1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[1]" LOC = "G2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[1]" LOC = "F2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[2]" LOC = "N3" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[2]" LOC = "N2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[3]" LOC = "M8" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[3]" LOC = "L8" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_addr[14]" LOC = "D6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[13]" LOC = "B1" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[12]" LOC = "D8" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[11]" LOC = "D5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[10]" LOC = "F8" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[9]" LOC = "C2" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[8]" LOC = "G7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[7]" LOC = "A2" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[6]" LOC = "E6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[5]" LOC = "A4" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[4]" LOC = "E5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[3]" LOC = "B4" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[2]" LOC = "C4" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[1]" LOC = "F5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[0]" LOC = "B5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ba[2]" LOC = "C6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ba[1]" LOC = "E7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ba[0]" LOC = "A7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ck_p[0]" LOC = "F9" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ck_n[0]" LOC = "E8" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ras_n" LOC = "C7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_cas_n" LOC = "B7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_we_n" LOC = "B6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_reset_n" LOC = "B2" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ;
NET "ddr3_cke[0]" LOC = "F7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_odt[0]" LOC = "A3" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_cs_n[0]" LOC = "A5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
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預設配置
Summary，檢查一下，然後下一步。
點選Accept
點選Next
點選Generate
4.PS
新建PS
雙擊PS7的IP
先應用一個開發板的配置(ZedBoard)，這樣配置起來比較快
配置MIO
BANk0為3.3V，BANK1為1.8V
檢查各個外設是否與MIZ7035的核心板匹配
QSPI Flash，匹配
乙太網，匹配
USB，匹配
SD卡，WP訊號其實沒有用處，去掉，其他地方匹配
eMMC,需要新增SD1介面，CD和WP訊號無用，不需要新增
除錯串列埠，匹配
外設復位，ENET上電覆位；USB復位在PL上，而這裡只能選PS的MIO引腳，所以忽略；沒有I2C，取消掉。
其他預設
配置時鐘
輸入時鐘為33.333MHZ，匹配
CPU頻率改為666.666666MHz,DDR為533.333333MHz
其他預設
DDR配置
Memory Part選擇MT41K256M16 RE-125
DQS to Clock Delay全部寫0
Board Delay全部寫0.25
中斷配置
開啟PL-PS的IRQ_F2P的中斷功能
儲存
5.Block Design
點選Run Block Automation建立PS的介面
建立Clocking Wizard
雙擊IP進行配置，外部GCLK的100MHz時鐘，因為直接接入了時鐘引腳，選擇Global Buffer。
因為PL DDR3的參考時鐘配置的是200MHz，這裡讓MMCM輸出200MHz，並將Reset設定為低有效。
對埠進行連線
點選Run Connection Automation進行連線，
時鐘選擇/mmcm_mig7/clk_out1(200MHz)。
重新進行連線
新建IO約束檔案MIZ7035_IO.xdc
寫約束：
create_clock -name clk100m_i -period 10.00 [get_ports clk100m_i]
set_property VCCAUX_IO DONTCARE [get_ports clk100m_i]
set_property IOSTANDARD SSTL15 [get_ports clk100m_i]
set_property PACKAGE_PIN C8 [get_ports clk100m_i]
set_property PACKAGE_PIN H7 [get_ports rst_key]
set_property IOSTANDARD SSTL15 [get_ports rst_key]
set_property PACKAGE_PIN K10 [get_ports init_calib_complete]
set_property IOSTANDARD SSTL15 [get_ports init_calib_complete]
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右鍵點選BD,Create HDL Wrapper,
Generate Output Products
點選Generate Bitstream完成綜合、實現和生成bit。
可以檢視實現結果，MIG還是佔用了挺多資源的
6.SDK測試
切換到Block Design
File->Export->Export Hardware
勾選Include Bitstream
File->Launch SDK
開啟SDK，自動生成了hw資料夾
File->New->Application Project
新建測試ps dram的工程
選擇Zynq DRAM test
自動生成了bsp和程式的工程
Xilinx->Program FPGA
點選Program
然後右鍵點選工程目錄，選擇
Run As->Launch on Hardware
下載程式後通過串列埠即可對PS的DDR進行測試。
File->New->Application Project
新建測試pl dram的工程
選擇Memory Tests例程
編譯，下載FPGA的bit和程式的elf
即可看到對板上Memory的測試，包括了
PL的MIG控制的DDR,PS部分的DDR，以及OCM的RAM
7.總結
通過測試，掛在GP0埠上的1GB PL DDR3是可以進行訪問的，因為GP0使用的是200MHz匯流排，而且用到的是AXI4 Lite介面，所以速度比較慢。但是應該可以用來做視訊處理了。800MHz時鐘，相當於1600MHz的DDR3訪問速度，應該是比PS端1066MHz的DDR3存取速度要快