Coverage Overview

• 隨著芯片規模越來越大，集成的功能越來越多，一次性流片費用的增加，市場競爭的日益激烈，如何在驗證和測試中解決判斷驗證充分性和完備性的問題逐步成為業界驗證工作的熱門話題。

• 並且伴隨驗證技術的進一步發展，驗證技術也發生了巨大的變化，覆蓋率作為其中一種判斷驗證充分性的手段已經被廣泛的應用在集成電路的設計驗證工作中。

• 本文將主要介紹設計驗證工作中經常遇到的覆蓋率的基本概念，希望對需要的朋友有所幫助。

Test Coverage

• Fault Coverage consists of thepercentage of fault detected from among all faults that the test pattern settests-treating untestable faults the same as undetected faults.Tessent FastScancalculates test coverage using the formula:

NOTE

• DT(detected):all faults that the ATPGprocess identifies as detected.

• PD(possible-detected):all faults thatfault simulation identifies as possible-detected but not hard detected.

• TE(Testable):all those faults thatcannot be proven untestable.

• full:testable and un-testable

Conclusion

The 100% coverage does not necessarily indicate design correctness,or even that all bugs have been observed.The 100% coverage is a high degree of confidence that all important bugs have been found.On the other hand,different EDA tools may have different coverage sets,so you could get more information and examples from the tools’ help doc.Atlast,hope it can lend you a hand and pls scan the next page QR for moreinformation and materials.

RTL基本知識：關於coverage