網上搜了些資料，礙於智商和基礎，看不懂，

只有將S5PV210 資料手冊關於I2C的部分，翻譯記錄下，留到以後用。

1.OVERVIEW

The S5PV210 RISC microprocessor supports four multi-master I2C bus serial interfaces. To carry information
between bus masters and peripheral devices connected to the I2C bus, a dedicated Serial Data Line (SDA) and
an Serial Clock Line (SCL) 
 
is used. Both SDA and SCL lines are bi-directional.
210支援4個多主I2C序列介面。為了在主裝置和從裝置之間傳輸資料，需要使用一個專用的序列資料線和一個序列時鐘線。SDA和SCL都是雙向傳輸的。

In multi-master I2C-bus mode, multiple S5PV210 RISC microprocessors receive or transmit serial data to or from
slave devices. The master S5PV210 initiates and terminates a data transfer over the I2C bus. The I2C bus 
 
in the
S5PV210 uses a standard bus arbitration procedure.
在多主I2C匯流排模式中，多個210處理器接受或傳送資料和從裝置。主裝置210開始和結束資料的傳送在I2C總線上。I2C匯流排在210上使用一個標準的匯流排仲裁程式。

To control multi-master I2C-bus operations, values must be written to the following registers:
• Multi-master I2C-bus control register- I2CCON
• Multi-master I2C-bus control/status register- I2CSTAT
• Multi
 
-master I2C-bus Tx/Rx data shift register- I2CDS
• Multi-master I2C-bus address register- I2CADD
為了使用I2C操作，下面的暫存器必須被寫：
控制暫存器——I2CCON
控制/狀態暫存器——I2CSTAT
輸出/接受 移位暫存器——I2CDS
地址暫存器——I2CADD

If the I2C-bus is free, both SDA and SCL lines should be both at High level. A High-to-Low transition of SDA
initiates a Start condition. A Low-to-High transition of SDA initiates a Stop condition while SCL remains steady at
High Level.
如果I2C匯流排是空閒的，那麼SDA和SCL都應該處於高電平。SDA從高到低的轉換髮出一個開始條件。當SCL維持穩定的高電平時，SDA低到高變化發出一個停止訊號。

The master device always generates Start and Stop conditions. First 7-bit address value in the data byte that is
transferred via SDA line after the Start condition has been initiated, can determine the slave device which the bus
master device has selected. The 8th bit determines the direction of the transfer (read or write).
主裝置控制開始和結束。在起始訊號之後，剛開始的7個bit表示地址值，通過SDA傳輸，用來確定從裝置。第8bit確定傳輸的方向（讀/寫）

Every data byte put onto the SDA line should be eight bits in total. There is no limit to send or receive bytes during
the bus transfer operation. Data is always sent from most-significant bit (MSB) first, and every byte should be
immediately followed by acknowledge (ACK) bit.
所有放到SDA的位元組資料都應該總共使用8bit表示。在匯流排轉移操作期間，傳輸和接受位元組沒有限制。資料總是從最重要的位元組開始傳送，每位元組資料後應該立即有ACK。

2.KEY FEATURES OF IIC-BUS INTEFACE

• Four channel Multi-Master, Slave I2C BUS interfaces
(One channel for HDMI PHY is internally connected. Three channels can be used for general purpose.
However, if the user wants to use HDMI, it is recommended to allocate one channel for HDMI use only among
three channels)
• 7-bit addressing mode
• Serial, 8-bit oriented, and bidirectional data transfer
• Supports up to 100kbit/s in the Standard mode
• Supports up to 400kbit/s in the Fast mode.
• Supports master transmit, master receive, slave transmit and slave receive operation
• Supports interrupt or polling events
四個I2C介面（一個通道被內部連線，三個可以用於一般目的。然而，如果要使用HDMI，推薦在三個通道中分配一個用於HDMI）
7bit地址模式
序列，8bit單線，雙向資料傳輸
支援主傳送，主接受，從傳送，從接受
支援中斷、輪詢

3.IIC-BUS INTERFACE OPERATION

The S5PV210 I2C-bus interface has four operation modes, namely:
• Master Transmitter Mode
• Master Receive Mode
• Slave Transmitter Mode
• Slave Receive Mode
The functional relationships among these operating modes are described below
210 I2C 有四種操作模式，
主傳送
主接受
從傳送
從接受
這些模式的功能關係如下

5. START AND STOP CONDITIONS

If the I2C-bus interface is inactive, it is usually in Slave mode. In other words, the interface should be in Slave
mode before detecting a Start condition on the SDA line (a Start condition is initiated with a High-to-Low transition
of the SDA line while the clock signal of SCL is High). If the interface state is changed to Master mode, SDA line
initiates data transfer and generates SCL signal.
如果I2C處於空閒，那麼通常處於從模式。換句話，介面在檢查到起始訊號前應該處於從模式（當SCL處於高時，起始訊號通過SDA高變低發出）。如果介面狀態被改變成主模式，
SDA線發出資料，併產生SCL訊號

A Start condition transfers one-byte serial data via SDA line, and a Stop condition terminates the data transfer. A
Stop condition is a Low-to-High transition of the SDA line while SCL is High. The master generates Start and Stop
conditions. The I2C-bus gets busy if a Start condition is generated. On the other hand, a Stop condition frees the
I2C-bus.
一個起始訊號後傳輸一個位元組的序列資料通過SDA線，一個停止訊號後資料傳輸結束。停止訊號表現為SDA高變低，當SCL處於高時。主裝置產生起始和停止訊號。
如果起始訊號引數，那麼I2C匯流排處於忙狀態。另一方面，停止訊號後I2C處於空閒狀態

If a master initiates a Start condition, it should send a slave address to notify the slave device. One byte of
address field consists of a 7-bit address and a 1-bit transfer direction indicator (that shows write or read).
If bit 8 is 0, it indicates a write operation (Transmit Operation); if bit 8 is 1, it indicates a request for data read
(Receive Operation).
如果主裝置要發出一個開始訊號，他需要傳送一個從裝置地址通知從裝置。一個位元組長度的地址域，包含7bit的地址和1bit的傳輸方向（表示讀/寫）.
如果第8bit為0，則表示寫操作，如果為1，表示讀操作。

The master transmits Stop condition to complete the transfer operation. If the master wants to continue the data
transmission to the bus, it should generate another Start condition as well as a slave address. In this way, the
read-write operation is performed in various formats.
主裝置傳送停止訊號表示傳輸完成。如果主裝置想繼續傳輸資料，他應該產生其他的起始訊號以及從裝置地址。這樣，讀寫操作以各種方式執行。

6.DATA TRANSFER FORMAT

Every byte placed on the SDA line should be eight bits in length. There is no limit to transmit bytes per transfer.
The first byte following a Start condition should have the address field. If the I2C-bus is operating in Master mode,
master transmits the address field. Each byte should be followed by an acknowledgement (ACK) bit. The MSB bit
of the serial data and addresses are sent first.
SDA上的位元組長度應該為8bit。每一次傳輸，傳輸的位元組們都沒有限制。第一個位元組緊跟在起始位後，並且有地址域。如果I2C處於主模式，主裝置傳輸地址域。
每個位元組之後應跟著一位ACK.序列資料的MSB和地址是首先被傳輸的。

7.ACK SIGNAL TRANSMISSION

To complete a one-byte transfer operation, the receiver sends an ACK bit to the transmitter. The ACK pulse
occurs at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master
generates clock pulse required to transmit the ACK bit.
接收者傳送一個ACK給傳輸這，表示完成一位元組的傳輸操作。ACK脈衝發生在第九個SCL時鐘處。第八個時鐘被接受，為了一位元組資料的傳輸。
主裝置產生的時鐘脈衝被接受用於傳輸ACKbit。

The transmitter sets the SDA line to High to release the SDA line if the ACK clock pulse is received. The receiver
drives the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the
ninth SCL pulse. The software (I2CSTAT) enables or disables ACK bit transmit function. However, the ACK pulse
on the ninth clock of SCL is required to complete the one-byte data transfer operation.
如果ACK時鐘脈衝被接受，那麼傳送者拉高SDA來表示釋放SDA。在ACK時鐘脈衝期間，接收者驅動SDA拉低，因此，SDA本應該在SCL的第九個脈衝時期保持高 ，
但卻保持低。軟體方式（I2CSTAT）可以使能或禁止ACKbit傳輸功能。然而，在SCL的第九個脈衝時需要ACK脈衝用來表示一個位元組資料傳輸操作完成。

8.READ-WRITE OPERATION

In data is transmitted in Transmitter mode, the I2C-bus interface waits until I2C-bus Data Shift (I2CDS) register
receives the new data. Before the new data is written to the register, the SCL line is held low. The line is only
released after the data has been written. S5PV210 holds the interrupt to identify the completion of current data
transfer. After the CPU receives the interrupt request, it writes new data to the I2CDS register again.
當資料被傳輸完後，並處於傳送模式，I2C介面會進行等待狀態，直到I2C資料移位暫存器（I2CDS）收到新的資料。在新資料被寫到暫存器之前，SCL保持低。
當資料被寫完後，SCL才被釋放。S5PV210使用中斷來確定當前資料傳輸完成。CPU收到中斷請求後，他會再次寫新的資料到I2CDS暫存器。

If data is received in Receive mode, the I2C-bus interface waits until I2CDS register is read. Before the new data
is read out, the SCL line is held low. The line is only released after the data has been read. S5PV210 holds the
interrupt to identify the completion of new data reception. After the CPU receives the interrupt request, it reads the
data from the I2CDS register.
當處於接受模式，資料被接受完後，I2C介面會進入等待模式，直到I2CDS暫存器被讀。在新的資料被讀出前，SCL會保持低。只有當資料已經被讀後，SCL才被釋放。
S5PV210使用中斷取識別新資料接受完成。在CPU接受到中斷請求後，他會從I2CDS暫存器中讀資料。