Zedboard & Zynq 影象採集 視訊開發 (二) FPGA影象採集raw轉rgb888
阿新 • • 發佈：2019-02-05
前一篇已經介紹了Zedboard上面搭建影象採集系統的硬體結構，這一篇主要介紹Zynq內部Fpga部分系統設計
下面是在本工程的系統框圖
影象採集
OV7725是一款CMOS影象感測器，VGA解析度，幀率60fps，SCCB協議，與I2C協議通用。這裡用HDL編寫一個I2C 模組，對ov7725進行初始化，i2c模組是直接採用的crazybingo的設計，這裡不再贅述，只是列出ov7725暫存器初始化列表，讓其輸出Bayer RGB影象資料- 0 : LUT_DATA = {8'h1C, 8'h7F}; //Manufacturer ID Byte - High (Read only)
- 1 : LUT_DATA = {8'h1D, 8'hA2}; //Manufacturer ID Byte - Low (Read only)
- //Write Data Index
- 2 : LUT_DATA = {8'h12, 8'h80}; // BIT[7]-Reset all the Reg
- 3 : LUT_DATA = {8'h3d, 8'h03}; //DC offset for analog process
- 4 : LUT_DATA = {8'h15, 8'h02}; //COM10: href/vsync/pclk/data reverse(Vsync H valid)
- 5 : LUT_DATA = {8'h17, 8'h22}; //VGA: 8'h22; QVGA: 8'h3f;
- 6 : LUT_DATA = {8'h18, 8'ha4}; //VGA: 8'ha4; QVGA: 8'h50;
- 7 : LUT_DATA = {8'h19, 8'h07}; //VGA: 8'h07; QVGA: 8'h03;
- 8 : LUT_DATA = {8'h1a, 8'hf0}; //VGA: 8'hf0; QVGA: 8'h78;
- 9 : LUT_DATA = {8'h32, 8'h00}; //Bit[7]:Mirror image edge alignment
- 10 : LUT_DATA = {8'h29, 8'hA0}; //VGA: 8'hA0; QVGA: 8'hF0
- 11 : LUT_DATA = {8'h2C, 8'hF0}; //VGA: 8'hF0; QVGA: 8'h78
- 12 : LUT_DATA = {8'h0d, 8'h41}; //Bypass PLL
- 13 : LUT_DATA = {8'h11, 8'h01}; //CLKRC,Finternal clock = Finput clk*PLL multiplier/[(CLKRC[5:0]+1)*2] = 25MHz*4/[(x+1)*2]
- //00: 50fps, 01:25fps, 03:12.5fps (50Hz Fliter)
- 14 : LUT_DATA = {8'h12, 8'h03}; //BIT[6]: 0:VGA; 1;QVGA
- //BIT[3:2]: 01:RGB565
- //VGA: 00:YUV; 01:Processed Bayer RGB; 10:RGB; 11:Bayer RAW; BIT[7]-Reset all the Reg
- 15 : LUT_DATA = {8'h0c, 8'h90}; //COM3: Bit[6]:Horizontal mirror image ON/OFF, Bit[0]:Color bar; Default:8'h10
- //DSP control
- 16 : LUT_DATA = {8'h42, 8'h7f}; //BLC Blue Channel Target Value, Default: 8'h80
- 17 : LUT_DATA = {8'h4d, 8'h09}; //BLC Red Channel Target Value, Default: 8'h80
- 18 : LUT_DATA = {8'h63, 8'hf0}; //AWB Control
- 19 : LUT_DATA = {8'h64, 8'hff}; //DSP_Ctrl1:
- 20 : LUT_DATA = {8'h65, 8'h00}; //DSP_Ctrl2:
- 21 : LUT_DATA = {8'h66, 8'h00}; //{COM3[4](0x0C), DSP_Ctrl3[7]}:00:YUYV; 01:YVYU; [10:UYVY] 11:VYUY
- 22 : LUT_DATA = {8'h67, 8'h02}; //DSP_Ctrl4:[1:0]00/01: YUV or RGB; 10: RAW8; 11: RAW10
- //AGC AEC AWB
- 23 : LUT_DATA = {8'h13, 8'hff};
- 24 : LUT_DATA = {8'h0f, 8'hc5};
- 25 : LUT_DATA = {8'h14, 8'h11};
- 26 : LUT_DATA = {8'h22, 8'h98}; //Banding Filt er Minimum AEC Value; Default: 8'h09
- 27 : LUT_DATA = {8'h23, 8'h03}; //Banding Filter Maximum Step
- 28 : LUT_DATA = {8'h24, 8'h40}; //AGC/AEC - Stable Operating Region (Upper Limit)
- 29 : LUT_DATA = {8'h25, 8'h30}; //AGC/AEC - Stable Operating Region (Lower Limit)
- 30 : LUT_DATA = {8'h26, 8'ha1}; //AGC/AEC Fast Mode Operating Region
- 31 : LUT_DATA = {8'h2b, 8'h9e}; //TaiWan: 8'h00:60Hz Filter; Mainland: 8'h9e:50Hz Filter
- 32 : LUT_DATA = {8'h6b, 8'haa}; //AWB Control 3
- 33 : LUT_DATA = {8'h13, 8'hff}; //8'hff: AGC AEC AWB Enable; 8'hf0: AGC AEC AWB Disable;
- //matrix sharpness brightness contrast UV
- 34 : LUT_DATA = {8'h90, 8'h0a};
- 35 : LUT_DATA = {8'h91, 8'h01};
- 36 : LUT_DATA = {8'h92, 8'h01};
- 37 : LUT_DATA = {8'h93, 8'h01};
- 38 : LUT_DATA = {8'h94, 8'h5f};
- 39 : LUT_DATA = {8'h95, 8'h53};
- 40 : LUT_DATA = {8'h96, 8'h11};
- 41 : LUT_DATA = {8'h97, 8'h1a};
- 42 : LUT_DATA = {8'h98, 8'h3d};
- 43 : LUT_DATA = {8'h99, 8'h5a};
- 44 : LUT_DATA = {8'h9a, 8'h1e};
- 45 : LUT_DATA = {8'h9b, 8'h3f}; //Brightness
- 46 : LUT_DATA = {8'h9c, 8'h25};
- 47 : LUT_DATA = {8'h9e, 8'h81};
- 48 : LUT_DATA = {8'ha6, 8'h06};
- 49 : LUT_DATA = {8'ha7, 8'h65};
- 50 : LUT_DATA = {8'ha8, 8'h65};
- 51 : LUT_DATA = {8'ha9, 8'h80};
- 52 : LUT_DATA = {8'haa, 8'h80};
- //Gamma correction
- 53 : LUT_DATA = {8'h7e, 8'h0c};
- 54 : LUT_DATA = {8'h7f, 8'h16}; //
- 55 : LUT_DATA = {8'h80, 8'h2a};
- 56 : LUT_DATA = {8'h81, 8'h4e};
- 57 : LUT_DATA = {8'h82, 8'h61};
- 58 : LUT_DATA = {8'h83, 8'h6f};
- 59 : LUT_DATA = {8'h84, 8'h7b};
- 60 : LUT_DATA = {8'h85, 8'h86};
- 61 : LUT_DATA = {8'h86, 8'h8e};
- 62 : LUT_DATA = {8'h87, 8'h97};
- 63 : LUT_DATA = {8'h88, 8'ha4};
- 64 : LUT_DATA = {8'h89, 8'haf};
- 65 : LUT_DATA = {8'h8a, 8'hc5};
- 66 : LUT_DATA = {8'h8b, 8'hd7};
- 67 : LUT_DATA = {8'h8c, 8'he8};
- 68 : LUT_DATA = {8'h8d, 8'h20};
- //Others
- 69 : LUT_DATA = {8'h0e, 8'h65};//night mode auto frame rate control
Bayer8轉RGB888
ov7725影象感測器可以輸出rgb565，yuv格式的影象資料，但這裡用到的是RAW格式影象資料。配置好ov7725以後，攝像頭傳回raw格式影象資料，每個畫素8bit，Bayer畫素排列如下
畫素總數的一半是G分量，四分之一是R，四分之一是B，這是因為人眼對綠色分量最為敏感，所以G分量佔的比重大。將Bayer raw影象轉換為RGB影象，最簡單的辦法就是使用插值法，插值法就是使用周圍鄰域畫素來恢復自身畫素值的辦法，本設計採用3X3視窗來做雙線性插值，舉例說明，對於畫素點G22，綠色分量就等於自身畫素值，紅色分量R22 = (R12 + R32) / 2 藍色分量 B22 = (B21 + B23) / 2 以此類推線性插值法簡單，而且適合FPGA上面流水線操作，但是也有比較嚴重的弊端，那就是色彩的恢復沒有考慮到各個顏色分量之間的相關性，容易產生偽彩色，同時在影象紋理比較豐富的地方，容易造成影象輪廓失真。在FPGA上面實現雙線性插值法，要對影象進行3行的快取，這是FPGA影象處理比較基本的東西，也不再多說，只是提一下這件事，一些人在使用Altera FPGA的時候，quartus提供這樣一個IP
實際上就是多維的移位暫存器，但是在xilinx的ip中並沒有這個ip，只有一維的ram based shift register，不過不要緊，只要將多個一維移位暫存器串接起來就可以實現相同的功能了，當然也可以使用sysgen或者hls自己做一個（個人想法，沒有實現過）做好移位暫存器，就可以生成3X3矩陣，然後線性插值將RAW8轉換為RGB888了，具體過程可以參見我的工程：http://download.csdn.net/detail/zhangyu_eeprom/7726541