linux音頻alsa-uda134x驅動分析之二（時鐘)
阿新 • • 發佈：2017-11-07
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Master Clock
主時鐘
------------
Every audio subsystem is driven by a master clock (sometimes referred to as MCLK or SYSCLK). This audio master clock can be derived from a number of sources (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
audio playback and capture sample rates.
每個數字音頻子系統都是由主時鐘來驅動的（有時稱為MCLK或SYSCLK）。音頻主時鐘可以派生於多種源（如晶振，鎖相環，處理器時鐘）。負責產生正確的音頻播放和捕獲采樣率。
Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
their speed can be altered by software (depending on the system use and to save
power). Other master clocks are fixed at a set frequency (i.e. crystals).
有些主時鐘是可配置的（如基於鎖相環或處理器的時鐘），它們可以通過軟件改變速度（依賴於系統應用和省電的考慮）。另一些主時鐘則是固定於一個特定的頻率值（如晶振）。
數字音頻時鐘
----------
The Digital Audio Interface is usually driven by a Bit Clock (often referred
as BCLK). This clock is used to drive the digital audio data across the link
between the codec and CPU.
數字音頻接口往往是由一個位時鐘來驅動的（通常記為BCLK）。這個時鐘用於驅動數字音頻數據在解碼器與處理器間的傳輸。
The DAI also has a frame clock to signal the start of each audio frame. This
clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
runs at exactly the sample rate (LRC = Rate).
數字音頻接口還有一個幀時鐘，用來指示一幀音頻的開始。該時鐘有時記為LRC（left right clock）或FRAME。該時鐘嚴格工作於采樣率上。
Bit Clock can be generated as follows:-
位時鐘可以有如下產生方式：
BCLK = MCLK / x
or
BCLK = LRC * x
or
This relationship depends on the codec or SoC CPU in particular. In general
it is best to configure BCLK to the lowest possible speed (depending on your
rate, number of channels and word size) to save on power.
這個關系依賴於解碼器，特別是板上處理器。大體上講，最好將位時鐘盡可能低速（取決於你的采樣率，通道數和字長）以省電。
It is also desirable to use the codec (if possible) to drive (or master) the
audio clocks as it usually gives more accurate sample rates than the CPU.
可能的話，最好使用解碼器來驅動（或控制）音頻時鐘，因為通常它給出的采樣率比處理器更精確。
Audio Clocking
音頻時鐘
==============
This text describes the audio clocking terms in ASoC and digital audio in
general. Note: Audio clocking can be complex!
本文本總體描述ASoC和數字音頻中的音頻時鐘條款。
Master Clock
主時鐘
------------
Every audio subsystem is driven by a master clock (sometimes referred to as MCLK or SYSCLK). This audio master clock can be derived from a number of sources (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
audio playback and capture sample rates.
每個數字音頻子系統都是由主時鐘來驅動的（有時稱為MCLK或SYSCLK）。音頻主時鐘可以派生於多種源（如晶振，鎖相環，處理器時鐘）。負責產生正確的音頻播放和捕獲采樣率。
Some master clocks (e.g. PLLs and CPU based clocks) are configurable in that
their speed can be altered by software (depending on the system use and to save
power). Other master clocks are fixed at a set frequency (i.e. crystals).
有些主時鐘是可配置的（如基於鎖相環或處理器的時鐘），它們可以通過軟件改變速度（依賴於系統應用和省電的考慮）。另一些主時鐘則是固定於一個特定的頻率值（如晶振）。
|
數字音頻時鐘
----------
|
as BCLK). This clock is used to drive the digital audio data across the link
between the codec and CPU.
數字音頻接口往往是由一個位時鐘來驅動的（通常記為BCLK）。這個時鐘用於驅動數字音頻數據在解碼器與處理器間的傳輸。
The DAI also has a frame clock to signal the start of each audio frame. This
clock is sometimes referred to as LRC (left right clock) or FRAME. This clock
runs at exactly the sample rate (LRC = Rate).
數字音頻接口還有一個幀時鐘，用來指示一幀音頻的開始。該時鐘有時記為LRC（left right clock）或FRAME。該時鐘嚴格工作於采樣率上。
Bit Clock can be generated as follows:-
位時鐘可以有如下產生方式：
BCLK = MCLK / x
or
BCLK = LRC * x
or
This relationship depends on the codec or SoC CPU in particular. In general
it is best to configure BCLK to the lowest possible speed (depending on your
rate, number of channels and word size) to save on power.
這個關系依賴於解碼器，特別是板上處理器。大體上講，最好將位時鐘盡可能低速（取決於你的采樣率，通道數和字長）以省電。
It is also desirable to use the codec (if possible) to drive (or master) the
audio clocks as it usually gives more accurate sample rates than the CPU.
可能的話，最好使用解碼器來驅動（或控制）音頻時鐘，因為通常它給出的采樣率比處理器更精確。
linux音頻alsa-uda134x驅動分析之二（時鐘)