https://www.cnblogs.com/OneFri/p/6045041.html

• 四位加法器
• 兩級加法實現

verilog code

module  pipeliningadder(
                        output    reg     [3:0]    s,
                        output    reg              co,
                        input             [3:0]    a,
                        input             [3:0]    b,
                        input                      ci,

                        input                      clk,
                        input                      rstn
                        );

reg    [3:0]       a_tmp;
reg    [3:0]       b_tmp;
reg    [1:0]       a_tmp2;
reg    [1:0]       b_tmp2;
reg                ci_tmp;
reg    [1:0]       s_tmp3;

reg                co_low;
reg    [1:0]       s_low;
reg                co_hign;
reg    [1:0]       s_hign;


 
[email protected](posedge  clk,negedge  rstn)
begin
    if(!rstn)
    begin
        a_tmp   <= 4'b0;
        b_tmp   <= 4'b0;
        ci_tmp  <= 1'b0;
    end
    else
    begin                   //將輸入的資料快取起來
        a_tmp  <= a; 
        b_tmp  <= b; 
        ci_tmp <= ci; 
    end
end

 
[email protected](posedge  clk,negedge  rstn)
begin
    if(!rstn)
    begin
        co_low  <=  1'b0;
        s_low   <=  2'b0; 
        a_tmp2  <=  2'b0; 
        b_tmp2  <=  2'b0; 
    end
    else
    begin                  //低兩位相加，快取高兩位
        {co_low,s_low} <= a_tmp[1:0] + b_tmp[1:0] + ci_tmp;
        a_tmp2 <= a_tmp[3:2];
        b_tmp2 <= b_tmp[3:2];
    end
end

 
[email protected](posedge  clk,negedge  rstn)
begin
    if(!rstn)
    begin
        co_hign <= 2'b0;
        s_hign  <= 2'b0;
    end
    else
    begin                   //高兩位相加及與之間的低兩位一併輸出
        {co_hign,s_hign} <= a_tmp2 + b_tmp2 + co_low;
        s_tmp3   <= s_low; //寄存上一級的結果
    end
end

[email protected](posedge  clk,negedge  rstn)
begin
    if(!rstn)
    begin
        co <= 1'b0;
        s  <= 4'b0;
    end
    else
    begin
        {co,s} = {co_hign,s_hign,s_tmp3}; //合併上兩級計算結果，輸出結果
    end
end

endmodule

testbench

module  pipeliningadder_tb;
wire      [3:0]       s;
wire                  co;
reg       [3:0]       a;
reg       [3:0]       b;
reg                   ci;

reg                   clk;
reg                   rstn;

initial
begin
    clk   = 0;
    rstn  = 0;
    @(posedge clk)   rstn = 1;
 
                     a = 4'b0000; b = 4'b0000; ci = 0; 
    @(posedge clk)   a = 4'b1111; b = 4'b1111; ci = 0; 
    @(posedge clk)   a = 4'b1100; b = 4'b1001; ci = 0; 
    @(posedge clk)   a = 4'b0111; b = 4'b0110; ci = 0; 
    @(posedge clk)   a = 4'b0101; b = 4'b0101; ci = 1; 
    @(posedge clk)   a = 4'b1110; b = 4'b1001; ci = 1; 
    @(posedge clk)   a = 4'b0010; b = 4'b0110; ci = 1; 
    @(posedge clk)   a = 4'b0110; b = 4'b1101; ci = 1; 
    @(posedge clk)   a = 4'b1110; b = 4'b1110; ci = 1; 
    @(posedge clk)   a = 4'b1100; b = 4'b0110; ci = 1; 
    @(posedge clk)   a = 4'b1100; b = 4'b0101; ci = 1; 
    @(posedge clk)   a = 4'b0011; b = 4'b1010; ci = 1; 
    @(posedge clk)   $finish;
end

always #5  clk = ~clk;

initial begin
  $fsdbDumpfile("test.fsdb");
  $fsdbDumpvars();
end

pipeliningadder u_pipeliningadder(
                                              .s(s),
                                              .co(co),
                                              .a(a),
                                              .b(b),
                                              .ci(ci),
                                              .clk(clk),
                                              .rstn(rstn)
                                              );

endmodule

verdi波形檢視

總結

使用流水線實現可以縮短關鍵路徑，以提高運算頻率，加快運算。
其他相關加法器實現方法：verilog 實現加法器

參考資料

[1]. 加法器的verilog實現

形而上者謂之道 形而下者謂之器。

分類: Verilog

標籤: verilog

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posted @ 2016-11-08 22:40 喬_木 閱讀(748) 評論(0) 編輯 收藏